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74FCT162374 PDF预览

74FCT162374

更新时间： 2024-10-27 22:37:03
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德州仪器 - TI /
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7页 64K
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16-Bit Registers

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74FCT162374 数据手册

 浏览型号74FCT162374的Datasheet PDF文件第2页浏览型号74FCT162374的Datasheet PDF文件第3页浏览型号74FCT162374的Datasheet PDF文件第4页浏览型号74FCT162374的Datasheet PDF文件第5页浏览型号74FCT162374的Datasheet PDF文件第6页浏览型号74FCT162374的Datasheet PDF文件第7页 
1CY74FCT162374T  
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT16374T  
CY74FCT162374T  
SCCS055 - August 1994 - Revised March 2000  
16-Bit Registers  
Features  
Functional Description  
• FCT-E speed at 3.7 ns  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Typical output skew < 250 ps  
• ESD > 2000V  
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)  
packages  
• Industrial temperature range of −40˚C to +85˚C  
• VCC = 5V ± 10%  
CY74FCT16374T and CY74FCT162374T are 16-bit D-type  
registers designed for use as buffered registers in high-speed,  
low power bus applications. These devices can be used as two  
independent 8-bit registers or as a single 16-bit register by  
connecting the output Enable (OE) and Clock (CLK) inputs.  
Flow-through pinout and small shrink packaging aid in  
simplifying board layout. The output buffers are designed with  
power-off disable feature that allows live insertion of boards.  
The CY74FCT16374T is ideally suited for driving  
high-capacitance loads and low-impedance backplanes.  
The CY74FCT162374T has 24-mA balanced output drivers  
with current limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce. The  
CY74FCT162374T is ideal for driving transmission lines.  
CY74FCT16374T Features:  
• 64 mA sink current, 32 mA source current  
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,  
TA = 25˚C  
CY74FCT162374T Features:  
• Balanced 24 mA output drivers  
• Reduced system switching noise  
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,  
TA= 25˚C  
Logic Block Diagrams  
Pin Configuration  
SSOP/TSSOP  
Top View  
1
2
3
4
48  
47  
46  
OE  
O
CLK  
1
1
1
D
1
1
1
2
O
D
2
1
1
GND  
O
GND  
D
45  
44  
43  
42  
41  
OE  
OE  
2
1
5
1
1
3
4
1
1
3
4
O
D
6
CLK  
CLK  
2
1
V
CC  
V
CC  
7
O
5
O
6
D
D
1
1
1
1
5
6
8
D
C
D
C
D
1
D
1
1
2
9
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
O
1
O
1
1
2
GND  
O
GND  
D
10  
11  
1
1
7
8
1
1
7
8
O
D
12  
13  
O
O
D
D
2
2
1
2
2
1
2
14  
15  
16  
17  
18  
2
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
GND  
GND  
O
3
O
4
D
D
2
2
3
FCT162374-1  
FCT162374-2  
2
2
4
V
CC  
V
CC  
O
5
D
5
19  
20  
21  
22  
23  
24  
30  
29  
28  
27  
26  
25  
2
2
2
2
O
6
D
6
GND  
O
GND  
D
2
2
7
8
2
7
8
O
D
2
2
OE  
CLK  
2
FCT162374-3  
Copyright © 2000, Texas Instruments Incorporated  
1234567

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