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74F8963

更新时间： 2024-10-03 22:49:47
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
10页 99K
描述
9-Bit latched bidirectional Futurebus transceivers open-collector

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74F8963 数据手册

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Philips Semiconductors FAST Products  
Product specification  
9-Bit latched bidirectional Futurebus transceivers  
(open-collector)  
74F8962/8963  
power consumption and a series diode on  
the drivers to reduce capacitive loading.  
FEATURES  
• Octal latched transceiver  
• Multiple GND pins minimize ground bounce  
• Glitch–free power up/power down  
Incident wave switching to 9Ω is guaranteed.  
The voltage swing is much less for BTL, so is  
its receiver threshold region, therefore noise  
margins are excellent.  
operation  
• Drives heavily loaded backplanes with  
equivalent load impedances down to 10Ω  
DESCRIPTION  
• High drive (100mA) open collector drivers  
The 74F8962 and 74F8963 are octal  
bidirectional latched transceivers and are  
intended to provide the electrical interface to  
a high performance wired-OR bus. The B port  
inverting drivers are low-capacitance open  
collector with controlled ramp and are  
designed to sink 100mA from 2 volts. The B  
port inverting receivers have a 150mV  
threshold region.  
on B port  
BTL offers low power consumption, low  
ground bounce, EMI and crosstalk, low  
capacitive loading, superior noise margin and  
low propagation delays. This results in a high  
bandwidth, reliable backplane.  
• Reduced voltage swing (1 volt) produces  
less noise and reduces power consumption  
• High speed operation enhances  
performance of backplane buses and  
facilitates incident wave switching  
The 74F8962 and 74F8963 A ports have TTL  
3-state drivers and TTL receivers with a latch  
function.  
• Compatible with IEEE 896 futurebus  
standards  
The B port interfaces to ‘Backplane  
Transceiver Logic’ (BTL). BTL features a  
reduced (1V to 2V) voltage swing for lower  
The 74F8963 is the non-inverting version of  
74F8962.  
• Built–in precision band–gap reference  
provides accurate receiver thresholds and  
improved noise immunity  
TYPE  
TYPICAL PROPAGATION DELAY  
TYPICAL SUPPLY CURRENT( TOTAL)  
74F8962  
74F8963  
6.5ns  
5.5ns  
90mA  
90mA  
ORDERING INFORMATION  
ORDER CODE  
DESCRIPTION  
COMMERCIAL RANGE  
= 5V ±10%, T = 0°C to +70°C  
V
CC  
amb  
1
44–pin Quad Flat Pack  
N74F8962Y, N74F8963Y  
N74F8962A, N74F8963A  
44–pin Plastic Leaded Chip Carrier  
Note to ordering information  
1. Flatpack package is not available at this time.  
INPUT AND OUTPUT LOADING AND FAN OUT TABLE  
74F (U.L.)  
HIGH/LOW  
LOAD VALUE  
HIGH/LOW  
PINS  
DESCRIPTION  
AI0 – AI8  
B0 – B8  
PNP latched inputs  
1.0/0.167  
5.0/0.167  
1.0/0.033  
1.0/0.033  
150/40  
20µA/100µA  
100µA/100µA  
20µA/20µA  
20µA/20µA  
3mA/24mA  
OC/100mA  
Data inputs with threshold circuitry  
Output enable inputs (active low)  
Latch enable inputs (active low)  
3–state outputs  
OEAB, OEBA  
LEAB, LEBA  
AO0 – AO8  
B0 – B8  
Open collector outputs  
OC/166.7  
Notes to input and output loading and fan out table  
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.  
2. OC = Open collector.  
1
March 11, 1993  
853–1425 09230  
1234567...10

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