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74F86DCQM PDF预览

74F86DCQM

更新时间: 2024-11-10 13:02:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
4页 51K
描述
XOR Gate, TTL, CDIP14,

74F86DCQM 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:DIP, DIP14,.3
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.65JESD-30 代码:R-XDIP-T14
JESD-609代码:e0逻辑集成电路类型:XOR GATE
湿度敏感等级:2A端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):250
电源:5 V认证状态:Not Qualified
施密特触发器:NO子类别:Gates
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30Base Number Matches:1

74F86DCQM 数据手册

 浏览型号74F86DCQM的Datasheet PDF文件第2页浏览型号74F86DCQM的Datasheet PDF文件第3页浏览型号74F86DCQM的Datasheet PDF文件第4页 
April 1988  
Revised July 1999  
74F86  
2-Input Exclusive-OR Gate  
General Description  
This device contains four independent gates, each of which  
performs the logic exclusive-OR function.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F86SC  
74F86SJ  
74F86PC  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Unit Loading/Fan Out  
U.L.  
Input IIH/IIL  
Pin Names  
Description  
HIGH/LOW  
Output IOH/IOL  
An, Bn  
On  
Inputs  
1.0/1.0  
50/33.3  
20 µA/0.6 mA  
1 mA/20 mA  
Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS009470  
www.fairchildsemi.com  

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