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74F564SJ PDF预览

74F564SJ

更新时间: 2024-09-17 22:49:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 逻辑集成电路光电二极管驱动
页数 文件大小 规格书
6页 51K
描述
Octal D-Type Flip-Flop with 3-STATE Outputs

74F564SJ 数据手册

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April 1983  
Revised August 1999  
74F564  
Octal D-Type Flip-Flop with 3-STATE Outputs  
General Description  
Features  
The 74F564 is a high-speed, low power octal flip-flop with a  
buffered common Clock (CP) and a buffered common Out-  
put Enable (OE). The information presented to the D inputs  
is sorted in the flip-flops on the LOW-to-HIGH Clock (CP)  
transition.  
Inputs and outputs on opposite sides of package allow  
easy interface with microprocessors  
Useful as input or output port for microprocessors  
Functionally identical to 74F574  
3-STATE outputs for bus-oriented applications  
This device is functionally identical to the 74F574, but has  
inverted outputs.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F564SJ  
74F564PC  
M20D  
N20A  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009563  
www.fairchildsemi.com  

74F564SJ 替代型号

型号 品牌 替代类型 描述 数据表
74F564PC FAIRCHILD

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