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74F544SPC PDF预览

74F544SPC

更新时间: 2024-11-06 22:16:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 61K
描述
Octal Registered Transceiver

74F544SPC 数据手册

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April 1988  
Revised August 1999  
74F544  
Octal Registered Transceiver  
General Description  
Features  
The 74F544 octal transceiver contains two sets of D-type  
latches for temporary storage of data flowing in either  
direction. Separate Latch Enable and Output Enable inputs  
are provided for each register to permit independent con-  
trol of inputting and outputting in either direction of data  
flow. The A outputs are guaranteed to sink 24 mA while the  
B outputs are rated for 64 mA. The 74F544 inverts data in  
both directions.  
8-bit octal transceiver  
Back-to-back registers for storage  
Separate controls for data flow in each direction  
A outputs sink 24 mA, B outputs sink 64 mA  
Ordering Code:  
Order Number Package Number  
Package Description  
74F544SC  
M24B  
MSA24  
N24C  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide  
74F544MSA  
74F544SPC  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009555  
www.fairchildsemi.com  

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