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74F541SJ PDF预览

74F541SJ

更新时间: 2024-11-06 22:36:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
6页 58K
描述
Octal Buffer/Line Driver with 3-STATE Outputs

74F541SJ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.3
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.34
其他特性:WITH DUAL OUTPUT ENABLE控制类型:ENABLE LOW
系列:F/FASTJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.6 mm
逻辑集成电路类型:BUS DRIVER最大I(ol):0.064 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):75 mAProp。Delay @ Nom-Sup:6 ns
传播延迟(tpd):6 ns认证状态:Not Qualified
座面最大高度:2.1 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

74F541SJ 数据手册

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April 1988  
Revised August 1999  
74F540 • 74F541  
Octal Buffer/Line Driver with 3-STATE Outputs  
General Description  
Features  
The 74F540 and 74F541 are similar in function to the  
74F240 and 74F244 respectively, except that the inputs  
and outputs are on opposite sides of the package (see  
Connection Diagrams). This pinout arrangement makes  
these devices especially useful as output ports for micro-  
processors, allowing ease of layout and greater PC board  
density.  
3-STATE outputs drive bus lines  
Inputs and outputs opposite side of package, allowing  
easier interface to microprocessors  
Ordering Code:  
Order Number Package Number  
Package Description  
74F540SC  
74F540SJ  
74F540PC  
74F541SC  
74F541SJ  
74F541PC  
M20B  
M20D  
N20A  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagrams  
IEEE/IEC  
74F540  
74F540  
IEEE/IEC  
74F541  
74F541  
© 1999 Fairchild Semiconductor Corporation  
DS009553  
www.fairchildsemi.com  

74F541SJ 替代型号

型号 品牌 替代类型 描述 数据表
CY74FCT541TSOCTG4 TI

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