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74F377 PDF预览

74F377

更新时间: 2024-09-22 22:49:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器时钟
页数 文件大小 规格书
6页 65K
描述
Octal D-Type Flip-Flop with Clock Enable

74F377 数据手册

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April 1988  
Revised August 1999  
74F377  
Octal D-Type Flip-Flop with Clock Enable  
General Description  
Features  
The 74F377 has eight edge-triggered, D-type flip-flops with  
individual D inputs and Q outputs. The common buffered  
Clock (CP) input loads all flip-flops simultaneously, when  
the Clock Enable (CE) is LOW.  
Ideal for addressable register applications  
Clock enable for address and data synchronization  
applications  
Eight edge-triggered D-type flip-flops  
Buffered common clock  
The register is fully edge-triggered. The state of each D  
input, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
The CE input must be stable only one setup time prior to  
the LOW-to-HIGH clock transition for predictable operation.  
See 74F273 for master reset version  
See 74F373 for transparent latch version  
See 74F374 for 3-STATE version  
Ordering Code:  
Order Number Package Number  
Package Description  
74F377SC  
74F377SJ  
74F377PC  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009525  
www.fairchildsemi.com  

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