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74F273PCQR

更新时间: 2024-11-28 13:04:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
6页 63K
描述
D Flip-Flop, F/FAST Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, TTL, PDIP20, PLASTIC, DIP-20

74F273PCQR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.3
系列:F/FASTJESD-30 代码:R-PDIP-T20
JESD-609代码:e0长度:24.895 mm
逻辑集成电路类型:D FLIP-FLOP位数:8
功能数量:1端子数量:20
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):11 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:100 MHz
Base Number Matches:1

74F273PCQR 数据手册

 浏览型号74F273PCQR的Datasheet PDF文件第2页浏览型号74F273PCQR的Datasheet PDF文件第3页浏览型号74F273PCQR的Datasheet PDF文件第4页浏览型号74F273PCQR的Datasheet PDF文件第5页浏览型号74F273PCQR的Datasheet PDF文件第6页 
April 1988  
Revised August 1999  
74F273  
Octal D-Type Flip-Flop  
General Description  
Features  
Ideal buffer for MOS microprocessor or memory  
Eight edge-triggered D-type flip-flops  
Buffered common clock  
The 74F273 has eight edge-triggered D-type flip-flops with  
individual D inputs and Q outputs. The common buffered  
Clock (CP) and Master Reset (MR) inputs load and reset  
(clear) all flip-flops simultaneously.  
Buffered, asynchronous Master Reset  
See 74F377 for clock enable version  
See 74F373 for transparent latch version  
See 74F374 for 3-STATE version  
The register is fully edge-triggered. The state of each D  
input, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The  
device is useful for applications where the true output only  
is required and the Clock and Master Reset are common to  
all storage elements.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F273SC  
74F273SJ  
74F273PC  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009511  
www.fairchildsemi.com  

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