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74F191 PDF预览

74F191

更新时间: 2024-11-10 22:45:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器时钟
页数 文件大小 规格书
7页 80K
描述
Up/Down Binary Counter with Preset and Ripple Clock

74F191 数据手册

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April 1988  
Revised July 1999  
74F191  
Up/Down Binary Counter with Preset and Ripple Clock  
General Description  
Features  
The 74F191 is a reversible modulo-16 binary counter fea-  
turing synchronous counting and asynchronous presetting.  
The preset feature allows the 74F191 to be used in pro-  
grammable dividers. The Count Enable input, the Terminal  
Count output and Ripple Clock output make possible a  
variety of methods of implementing multistage counters. In  
the counting modes, state changes are initiated by the ris-  
ing edge of the clock.  
High-Speed—125 MHz typical count frequency  
Synchronous counting  
Asynchronous parallel load  
Cascadable  
Ordering Code:  
Order Number Package Number  
Package Description  
74F191SC  
74F191SJ  
74F191PC  
M16A  
M16D  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009495  
www.fairchildsemi.com  

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