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74F191_07 PDF预览

74F191_07

更新时间: 2024-09-18 04:28:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器时钟
页数 文件大小 规格书
12页 185K
描述
Up/Down Binary Counter with Preset and Ripple Clock

74F191_07 数据手册

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April 2007  
74F191  
Up/Down Binary Counter with Preset and Ripple Clock  
tm  
Features  
General Description  
High-Speed—125MHz typical count frequency  
Synchronous counting  
The 74F191 is a reversible modulo-16 binary counter  
featuring synchronous counting and asynchronous pre-  
setting. The preset feature allows the 74F191 to be used  
in programmable dividers. The Count Enable input, the  
Terminal Count output and Ripple Clock output make  
possible a variety of methods of implementing multistage  
counters. In the counting modes, state changes are initi-  
ated by the rising edge of the clock.  
Asynchronous parallel load  
Cascadable  
Ordering Information  
Order  
Number  
Package  
Number  
Package Description  
74F191SC  
74F191SJ  
74F191PC  
M16A  
M16D  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
©1988 Fairchild Semiconductor Corporation  
74F191 Rev. 1.0.2  
www.fairchildsemi.com  

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