5秒后页面跳转
74F175SJCX PDF预览

74F175SJCX

更新时间: 2024-01-02 17:47:23
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
12页 360K
描述
IC D FLIP-FLOP, FF/Latch

74F175SJCX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.3
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.52
系列:F/FASTJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:10.2 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:100000000 Hz最大I(ol):0.02 A
湿度敏感等级:1位数:4
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):34 mA
传播延迟(tpd):9.5 ns认证状态:Not Qualified
座面最大高度:2.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:5.3 mm最小 fmax:100 MHz
Base Number Matches:1

74F175SJCX 数据手册

 浏览型号74F175SJCX的Datasheet PDF文件第2页浏览型号74F175SJCX的Datasheet PDF文件第3页浏览型号74F175SJCX的Datasheet PDF文件第4页浏览型号74F175SJCX的Datasheet PDF文件第5页浏览型号74F175SJCX的Datasheet PDF文件第6页浏览型号74F175SJCX的Datasheet PDF文件第7页 
SN74F175  
QUADRUPLE D-TYPE FLIP-FLOP  
WITH CLEAR  
SDFS058B – D293, MARCH 1987 – REVISED MAY 2002  
D, N, OR NS PACKAGE  
(TOP VIEW)  
Contains Four Flip-Flops With Double-Rail  
Outputs  
Buffered Clock and Direct Clear Inputs  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CLR  
1Q  
1Q  
1D  
2D  
2Q  
2Q  
GND  
CC  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
4Q  
4Q  
4D  
3D  
3Q  
3Q  
CLK  
– Pattern Generators  
description  
This positive-edge-triggered flip-flop utilizes TTL  
circuitry to implement D-type flip-flop logic with a  
direct clear (CLR) input. Information at the data  
(D) inputs meeting setup-time requirements is  
transferred to outputs on the positive-going edge  
of the clock pulse. Clock triggering occurs at a  
particular voltage level and is not directly related  
to the transition time of the positive-going pulse.  
When the clock (CLK) input is at either the high or  
low level, the D-input signal has no effect at the  
output.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
SOIC – D  
SOP – NS  
Tube  
SN74F175N  
SN74F175N  
Tube  
SN74F175D  
0°C to 70°C  
F175  
Tape and reel  
Tape and reel  
SN74F175DR  
SN74F175NSR  
74F175  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
CLR  
L
CLK  
D
X
H
L
Q
L
Q
H
L
X
H
H
L
H
H
H
L
X
Q
Q
0
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

与74F175SJCX相关器件

型号 品牌 描述 获取价格 数据表
74F175SJX TI F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, 0.300 IN

获取价格

74F175SJX_NL FAIRCHILD D Flip-Flop, F/FAST Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output,

获取价格

74F1762A-T YAGEO Logic Circuit, TTL, PQCC44

获取价格

74F1763 NXP Intelligent DRAM controller IDC

获取价格

74F1764-1A NXP 1MX1, DRAM CONTROLLER, PQCC44

获取价格

74F1764-1N NXP IC 1M X 1, DRAM CONTROLLER, PDIP48, Memory Controller

获取价格