74F11

更新时间： 2024-01-24 06:19:16

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		栅
页数	文件大小	规格书
4页	51K
描述
Triple 3-Input AND Gate

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数据手册

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74F11 数据手册

April 1988

Revised July 1999

74F11

Triple 3-Input AND Gate

General Description

This device contains three independent gates, each of

which performs the logic AND function.

Ordering Code:

Order Number Package Number

Package Description

74F11SC

74F11SJ

74F11PC

M14A

M14D

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

IEEE/IEC

Unit Loading/Fan Out

Input I_IH/I_IL

U.L.

Pin Names

Description

Output I_OH/I_OL

HIGH/LOW

1.0/1.0

A_n, B_n, C_n

O_n

Inputs

20 µA/−0.6 mA

−1 mA/20 mA

Outputs

50/33.3

DS009459

www.fairchildsemi.com

12 3 4

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74F11_00	FAIRCHILD	获取价格	Triple 3-Input AND Gate
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74F112DCQM	FAIRCHILD	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDIP16,
74F112DCQR	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F112L1CQR	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F112PC	FAIRCHILD	获取价格	Dual JK Negative Edge-Triggered Flip-Flop
74F112PC_NL	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output