74CBTLV1G125

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74CBTLV1G125 数据手册

74CBTLV1G125

Single bus switch

Rev. 01 — 2 February 2007

Product data sheet

1. General description

The 74CBTLV1G125 is a high-performance, low-power, low-voltage, Si-gate CMOS

device, superior to most advanced CMOS compatible TTL families.

Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall

times across the entire V_CCrange from 2.3 V to 3.6 V.

This device is fully speciﬁed for partial power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

The 74CBTLV1G125 provides a single high-speed line switch. The switch is disabled

when the output enable (OE) input is high.

To ensure the high-impedance OFF-state during power up or power down, OE should be

tied to the V_CCthrough a pullup resistor. The minimum value of the resistor is determined

by the current-sinking capability of the driver.

2. Features

■ Supply voltage range from 2.3 V to 3.6 V

■ High noise immunity

■ Complies with JEDEC standard:

◆ JESD8-5 (2.3 V to 2.7 V)

◆ JESD8-B/JESD36 (2.7 V to 3.6 V).

■ ESD protection:

◆ HBM JESD22-A114-D exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

◆ CDM JESD22-C101-C exceeds 1000 V

■ 5 Ω switch connection between two ports

■ Rail to rail switching on data I/O ports

■ CMOS low power consumption

■ Latch-up performance meets requirements of JESD78 Class I

■ I_OFFcircuitry provides partial power down mode operation

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

12 3 4 5 6 7...18

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