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74CBTH16211DGGRE4

更新时间： 2024-11-05 08:03:19
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器开关逻辑集成电路光电二极管
页数 文件大小 规格书
9页 169K
描述
24-BIT FET BUS SWITCH WITH BUS HOLD

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74CBTH16211DGGRE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP56,.3,20针数：56
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.73其他特性：TTL COMPATIBLE BUS SWITCH
系列：CBT/FST/QS/5C/BJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：14 mm
逻辑集成电路类型：BUS DRIVER湿度敏感等级：1
位数：12功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：5 V传播延迟（tpd）：0.35 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

74CBTH16211DGGRE4 数据手册

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SN74CBTH16211  
24-BIT FET BUS SWITCH  
WITH BUS HOLD  
SCDS062C – JUNE 1998 – REVISED NOVEMBER 2001  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
5-Ω Switch Connection Between Two Ports  
TTL-Compatible Input Levels  
Bus Hold on Data Inputs/Outputs  
Eliminates the Need for External  
Pullup/Pulldown Resistors  
NC  
1A1  
1A2  
1A3  
1A4  
1A5  
1A6  
GND  
1A7  
1A8  
1OE  
2OE  
1B1  
1B2  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
1B9  
1B10  
1B11  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
2
3
4
description  
5
6
The SN74CBTH16211 provides 24 bits of  
high-speed TTL-compatible bus switching. The  
low on-state resistance of the switch allows  
connections to be made with minimal propagation  
delay.  
7
8
9
10  
11  
12  
13  
14  
1A9  
The device is organized as dual 12-bit bus  
switches with separate output-enable (OE)  
inputs. It can be used as two 12-bit bus switches  
or one 24-bit bus switch. When OE is low, the  
associated 12-bit bus switch is on, and the A port  
is connected to the B port. When OE is high, the  
switch is open, and a high-impedance state exists  
between the two ports.  
1A10  
1A11  
1A12  
2A1 15  
2A2  
42 1B12  
2B1  
2B2  
16  
17  
41  
40  
V
CC  
2A3 18  
GND 19  
2A4 20  
2A5 21  
2A6 22  
2A7 23  
2A8 24  
2A9 25  
2A10 26  
2A11 27  
2A12 28  
39 2B3  
38 GND  
37 2B4  
36 2B5  
35 2B6  
34 2B7  
33 2B8  
32 2B9  
31 2B10  
30 2B11  
29 2B12  
Active bus-hold circuitry is provided to hold  
unused or floating A and B ports at a valid logic  
level.  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
CC  
NC – No internal connection  
ORDERING INFORMATION  
ORDERABLE  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PART NUMBER  
SN74CBTH16211DL  
SN74CBTH16211DLR  
SN74CBTH16211DGGR  
SN74CBTH16211DGVR  
Tube  
SSOP – DL  
CBTH16211  
Tape and reel  
Tape and reel  
Tape and reel  
–40°C to 85°C  
TSSOP – DGG  
TVSOP – DGV  
CBTH16211  
CYH211  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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