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74AVC4T3144GU12 PDF预览

74AVC4T3144GU12

更新时间: 2024-11-29 11:12:19
品牌 Logo 应用领域
安世 - NEXPERIA 驱动逻辑集成电路
页数 文件大小 规格书
22页 273K
描述
4-bit dual-supply buffer/level translator; 3-stateProduction

74AVC4T3144GU12 技术参数

生命周期:Active包装说明:QCCN,
Reach Compliance Code:compliant风险等级:1.56
系列:AVCJESD-30 代码:R-PQCC-N12
长度:2 mm逻辑集成电路类型:BUS DRIVER
位数:4功能数量:1
端口数量:2端子数量:12
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCN
封装形状:RECTANGULAR封装形式:CHIP CARRIER
传播延迟(tpd):12.1 ns座面最大高度:0.5 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.2 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:NO LEAD端子位置:QUAD
宽度:1.7 mmBase Number Matches:1

74AVC4T3144GU12 数据手册

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74AVC4T3144  
4-bit dual-supply buffer/level translator; 3-state  
Rev. 2 — 24 July 2018  
Product data sheet  
1. General description  
The 74AVC4T3144 is a 4-bit, dual-supply level translating buffer with 3-state outputs. It features  
four data inputs (An and B4), four data outputs (YBn and YA4), and an output enable input (OE).  
The device is configured to translate three inputs from VCC(A) to VCC(B) and one input from VCC(B)  
to VCC(A). OE, An and YA4 are referenced to VCC(A) and YBn and B4 are referenced to VCC(B). A  
HIGH on OE causes the outputs to assume a high-impedance OFF-state.  
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry  
disables outputs, preventing any damaging backflow current through the device when it is powered  
down. In suspend mode when either VCC(A) or VCC(B) are at GND level, all outputs are in the high-  
impedance OFF-state.  
2. Features and benefits  
Wide supply voltage range:  
VCC(A): 0.8 V to 3.6 V  
VCC(B): 0.8 V to 3.6 V  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114E Class 3B exceeds 8000 V  
CDM JESD22-C101C exceeds 1000 V  
Maximum data rates:  
380 Mbit/s (≥ 1.8 V to 3.3 V translation)  
200 Mbit/s (≥ 1.1 V to 3.3 V translation)  
200 Mbit/s (≥ 1.1 V to 2.5 V translation)  
200 Mbit/s (≥ 1.1 V to 1.8 V translation)  
150 Mbit/s (≥ 1.1 V to 1.5 V translation)  
100 Mbit/s (≥ 1.1 V to 1.2 V translation)  
Suspend mode  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Inputs accept voltages up to 3.6 V  
IOFF circuitry provides partial Power-down mode operation  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

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