Datasheet > 74AUP1G32GM-Q100

74AUP1G32GM-Q100

更新时间： 2024-02-25 07:34:59

品牌	Logo	应用领域
安世 - NEXPERIA		逻辑集成电路
页数	文件大小	规格书
14页	227K
描述
Low-power 2-input OR-gate

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

74AUP1G32GM-Q100 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	unknown	风险等级：	5.59
JESD-609代码：	e4	逻辑集成电路类型：	OR GATE
湿度敏感等级：	1	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
Base Number Matches：	1

74AUP1G32GM-Q100 数据手册

74AUP1G32-Q100

Low-power 2-input OR-gate

Rev. 3 — 28 January 2019

Product data sheet

1. General description

The 74AUP1G32-Q100 provides the single 2-input OR function.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times

across the entire V_CCrange from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire V_CCrange

from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the damaging backflow current through the device when it is

powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Wide supply voltage range from 0.8 V to 3.6 V

High noise immunity

Complies with JEDEC standards:

•

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8-B (2.7 V to 3.6 V)

•

ESD protection:

•

MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V

HBM JESD22-A114F Class 3A. Exceeds 5000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

•

Low static power consumption; I_CC= 0.9 µA (maximum)

Latch-up performance exceeds 100 mA per JESD 78 Class II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of V_CC

I_OFFcircuitry provides partial power-down mode operation

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74AUP1G32GW-Q100

74AUP1G32GM-Q100

-40 °C to +125 °C

TSSOP5

plastic thin shrink small outline package; 5 leads; SOT353-1

body width 1.25 mm

-40 °C to +125 °C

XSON6

plastic extremely thin small outline package;

no leads; 6 terminals; body 1 × 1.45 × 0.5 mm

SOT886

12 3 4 5 6 7...14

下载PDF

与74AUP1G32GM-Q100相关器件

型号	品牌	描述	获取价格	数据表
74AUP1G32GN	NXP	Low-power 2-input OR-gate	获取价格
74AUP1G32GN	NEXPERIA	Low-power 2-input OR-gateProduction	获取价格
74AUP1G32GS	NXP	Low-power 2-input OR-gate	获取价格
74AUP1G32GS	NEXPERIA	Low-power 2-input OR-gateProduction	获取价格
74AUP1G32GS,132	NXP	74AUP1G32 - Low-power 2-input OR-gate	获取价格
74AUP1G32GW	NXP	Low-power 2-input OR gate	获取价格