Datasheet > 驱动程序和接口 > 线路驱动器或接收器> 74AUP1G175

74AUP1G175

更新时间： 2024-11-05 04:00:55

品牌	Logo	应用领域
恩智浦 - NXP		线路驱动器或接收器驱动程序和接口接口集成电路
页数	文件大小	规格书
26页	92K
描述
Low-power D-type flip-flop with reset; positive-edge trigger

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74AUP1G175 技术参数

生命周期：	Active	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.57	Is Samacsys：	N
接口集成电路类型：	LINE DRIVER	Base Number Matches：	1

74AUP1G175 数据手册

74AUP1G175

Low-power D-type ﬂip-ﬂop with reset; positive-edge trigger

Rev. 01.mm — 27 March 2006

Preliminary data sheet

1. General description

The 74AUP1G175 is a high-performance, low-power, low-voltage, Si-gate CMOS device,

superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V_CCrange from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 0.8 V to 3.6 V.

This device is fully speciﬁed for partial Power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

The 74AUP1G175 is a single positive edge triggered D-type ﬂip-ﬂop with individual

data (D) input, clock (CP) input, master reset (MR) input, and Q output.The master reset

(MR) is an asynchronous active LOW input and operates independently of the clock input.

Information on the data input is transferred to the Q output on the LOW-to-HIGH transition

of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH

clock transition, for predictable operation.

2. Features

■ Wide supply voltage range from 0.8 V to 3.6 V

■ High noise immunity

■ Complies with JEDEC standards:

◆ JESD8-12 (0.8 V to 1.3 V)

◆ JESD8-11 (0.9 V to 1.65 V)

◆ JESD8-7 (1.2 V to 1.95 V)

◆ JESD8-5 (1.8 V to 2.7 V)

◆ JESD8-B (2.7 V to 3.6 V)

■ ESD protection:

◆ HBM JESD22-A114-C Class 3A. Exceeds 5000 V

◆ MM JESD22-A115-A exceeds 200 V

◆ CDM JESD22-C101-C exceeds 1000 V

■ Low static power consumption; I_CC= 0.9 µA (maximum)

■ Latch-up performance exceeds 100 mA per JESD 78 Class II

■ Inputs accept voltages up to 3.6 V

■ Low noise overshoot and undershoot < 10 % of V_CC

■ I_OFFcircuitry provides partial Power-down mode operation

12 3 4 5 6 7...26

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与74AUP1G175相关器件

型号	品牌	获取价格	描述	数据表
74AUP1G175GF	NXP	获取价格	Low-power D-type flip-flop with reset; positive-edge trigger
74AUP1G175GF,132	NXP	获取价格	74AUP1G175 - Low-power D-type flip-flop with reset; positive-edge trigger SON 6-Pin
74AUP1G175GM	NXP	获取价格	Low-power D-type flip-flop with reset; positive-edge trigger
74AUP1G175GM	NEXPERIA	获取价格	Low-power D-type flip-flop with reset; positive-edge triggerProduction
74AUP1G175GM,114	NXP	获取价格	74AUP1G175 - Low-power D-type flip-flop with reset; positive-edge trigger SON 6-Pin
74AUP1G175GM,115	NXP	获取价格	74AUP1G175 - Low-power D-type flip-flop with reset; positive-edge trigger SON 6-Pin
74AUP1G175GM,132	NXP	获取价格	74AUP1G175 - Low-power D-type flip-flop with reset; positive-edge trigger SON 6-Pin
74AUP1G175GM-G	NXP	获取价格	Low-power D-type flip-flop with reset; positive-edge trigger
74AUP1G175GN	NEXPERIA	获取价格	Low-power D-type flip-flop with reset; positive-edge triggerProduction
74AUP1G175GS	NEXPERIA	获取价格	Low-power D-type flip-flop with reset; positive-edge triggerProduction

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