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74AUP1G125DBVRG4 PDF预览

74AUP1G125DBVRG4

更新时间： 2024-11-07 08:03:11
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
24页 976K
描述
LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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74AUP1G125DBVRG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOT-23包装说明：LSSOP, TSOP5/6,.11,37
针数：5Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.41
Is Samacsys：N控制类型：ENABLE LOW
系列：AUP/ULP/VJESD-30 代码：R-PDSO-G5
JESD-609代码：e4长度：2.9 mm
负载电容（CL）：30 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.0017 A湿度敏感等级：1
位数：1功能数量：1
端口数量：2端子数量：5
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装等效代码：TSOP5/6,.11,37封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：1.2/3.3 V
Prop。Delay @ Nom-Sup：21.4 ns传播延迟（tpd）：21.4 ns
认证状态：Not Qualified座面最大高度：1.45 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.95 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：1.6 mmBase Number Matches：1

74AUP1G125DBVRG4 数据手册

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SN74AUP1G125  
www.ti.com  
SCES595J –JULY 2004–REVISED MARCH 2010  
LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT  
Check for Samples: SN74AUP1G125  
1
FEATURES  
•
•
•
Available in the Texas Instruments NanoStar™  
Package  
•
•
•
Wide Operating VCC Range of 0.8 V to 3.6 V  
Optimized for 3.3-V Operation  
Low Static-Power Consumption  
(ICC = 0.9 mA Max)  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Dynamic-Power Consumption  
(Cpd = 4 pF Typ at 3.3 V)  
•
•
•
tpd = 4.6 ns Max at 3.3 V  
Suitable for Point-to-Point Applications  
•
•
Low Input Capacitance (CI = 1.5 pF Typ)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
•
•
•
Input-Disable Feature Allows Floating Input  
Conditions  
–
2000-V Human-Body Model  
(A114-B, Class II)  
Ioff Supports Partial-Power-Down Mode  
Operation  
–
1000-V Charged-Device Model (C101)  
Input Hysteresis Allows Slow Input Transition  
and Better Switching Noise Immunity at Input  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
1
2
3
5
OE  
VCC  
OE  
A
VCC  
1
2
3
5
1
2
3
5
OE  
A
VCC  
A
4
GND  
Y
4
GND  
Y
4
Y
GND  
DSF PACKAGE  
(TOP VIEW)  
YFP PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(TOP VIEW)  
DRY PACKAGE  
(TOP VIEW)  
1
2
3
6
5
4
A2  
A2  
OE  
A
A1  
B1  
1
2
6
5
4
A1  
B1  
1
2
5
V
OE  
A
VCC  
OE  
A
VCC  
Y
1
2
3
6
5
4
CC  
OE  
VCC  
N.C.  
Y
B2  
C2  
DNU  
Y
N.C.  
Y
A
C1 3  
C1 3  
4
C2  
GND  
GND  
GND  
GND  
N.C. – No internal connection.  
DNU – Do not use  
See mechancial drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figure 1 and Figure 2).  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2010, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...24

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74AUP1G125DBVRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUP1G125DBVR TI

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