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74AUC1G125DBVRE4 PDF预览

74AUC1G125DBVRE4

更新时间： 2024-11-02 04:00:55
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
12页 358K
描述
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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74AUC1G125DBVRE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOT-23
包装说明：SOT-23, 5 PIN针数：5
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：5.3
Is Samacsys：N控制类型：ENABLE LOW
计数方向：UNIDIRECTIONAL系列：AUC
JESD-30 代码：R-PDSO-G5JESD-609代码：e4
长度：2.9 mm负载电容（CL）：15 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.009 A
湿度敏感等级：1位数：1
功能数量：1端口数量：2
端子数量：5最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LSSOP封装等效代码：TSOP5/6,.11,37
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：1.2/2.5 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：3.6 ns传播延迟（tpd）：3.6 ns
认证状态：Not Qualified座面最大高度：1.45 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.95 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：1.6 mm
Base Number Matches：1

74AUC1G125DBVRE4 数据手册

 浏览型号74AUC1G125DBVRE4的Datasheet PDF文件第2页浏览型号74AUC1G125DBVRE4的Datasheet PDF文件第3页浏览型号74AUC1G125DBVRE4的Datasheet PDF文件第4页浏览型号74AUC1G125DBVRE4的Datasheet PDF文件第5页浏览型号74AUC1G125DBVRE4的Datasheet PDF文件第6页浏览型号74AUC1G125DBVRE4的Datasheet PDF文件第7页 
SN74AUC1G125  
SINGLE BUS BUFFER GATE  
WITH 3-STATE OUTPUT  
www.ti.com  
SCES382K–MARCH 2002–REVISED APRIL 2007  
FEATURES  
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
Low Power Consumption, 10-µA Max ICC  
±8-mA Output Drive at 1.8 V  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
ESD Protection Exceeds JESD 22  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
•
•
Sub-1-V Operable  
1000-V Charged-Device Model (C101)  
Max tpd of 2.5 ns at 1.8 V  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRY PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
3
2
1
4
Y
VCC  
GND  
A
OE  
A
1
2
3
6
5
4
1
2
3
5
OE  
A
VCC  
NC  
Y
1
2
3
5
OE  
A
VCC  
5
VCC  
OE  
GND  
4
GND  
Y
4
Y
GND  
NC – No internal connection  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC  
operation.  
The SN74AUC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable  
(OE) input is high.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
ORDERING INFORMATION  
TA  
PACKAGE(1)(2)  
ORDERABLE PART NUMBER TOP-SIDE MARKING(3)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SON – DRY  
Reel of 3000  
SN74AUC1G125YZPR  
_ _ _UM_  
Reel of 5000  
Reel of 3000  
Reel of 3000  
SN74AUC1G125DRYR  
SN74AUC1G125DBVR  
SN74AUC1G125DCKR  
PREVIEW  
U25_  
–40°C to 85°C  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
UM_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
(3) DBV/DCK/DRY: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
UNLESS OTHERWISE NOTED this document contains  
Copyright © 2002–2007, Texas Instruments Incorporated  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...12

中文翻译

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74AUC1G125DBVRE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC1G125YEPR TI

完全替代

 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AUC1G125DBVR TI

类似代替

 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AUC1G126DBVR TI

类似代替

 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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