5秒后页面跳转
74ALVCHR16409PF8 PDF预览

74ALVCHR16409PF8

更新时间: 2024-11-06 20:53:35
品牌 Logo 应用领域
艾迪悌 - IDT 输入元件光电二极管逻辑集成电路电视
页数 文件大小 规格书
8页 84K
描述
TVSOP-56, Reel

74ALVCHR16409PF8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TVSOP
包装说明:TSSOP,针数:56
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.92其他特性:BUS HOLD INPUTS
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:11.3 mm
逻辑集成电路类型:BUS EXCHANGER湿度敏感等级:1
位数:18功能数量:1
端口数量:4端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240传播延迟(tpd):7 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.4 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

74ALVCHR16409PF8 数据手册

 浏览型号74ALVCHR16409PF8的Datasheet PDF文件第2页浏览型号74ALVCHR16409PF8的Datasheet PDF文件第3页浏览型号74ALVCHR16409PF8的Datasheet PDF文件第4页浏览型号74ALVCHR16409PF8的Datasheet PDF文件第5页浏览型号74ALVCHR16409PF8的Datasheet PDF文件第6页浏览型号74ALVCHR16409PF8的Datasheet PDF文件第7页 
3.3V CMOS 9-BIT, 4-PORT  
UNIVERSAL BUS EXCHANGER  
IDT74ALVCHR16409  
WITH 3-STATE OUTPUTS  
AND BUS-HOLD  
DESCRIPTION:  
FEATURES:  
This 9-bit, 4-port universal bus exchanger is built using advanced  
dual metal CMOS technology. The ALVCHR16409 allows synchronous  
data exchange between four different buses. Data flow is controlled by  
the select (SEL0–SEL4) inputs. A data-flow state is stored on the rising  
edge of the clock (CLK) input if the select-enable (SELEN) input is low.  
Once a data-flow state has been established, data is stored in the flip-flop  
on the rising edge of CLK if SELEN is high. The data-flow control logic is  
designed to allow glitch-free data transmission.  
0.5 MICRON CMOS Technology  
Typical tSK(0) (Output Skew) < 250ps  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.635mm pitch SSOP, 0.50mm pitch TSSOP,  
and 0.40mm pitch TVSOP packages  
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
When preset (PRE) transitions high, the outputs are disabled imme-  
diately without waiting for a clock pulse. To leave the high-impedance  
state, both PRE and SELEN must be low and a clock pulse must be  
applied.  
The ALVCHR16409 has been designed with a ±24mA output driver.  
This driver is capable of driving a moderate to heavy load while  
maintaining speed performance.  
Drive Features for ALVCHR16409:  
Balanced Output Drivers: ±12mA  
Low switching noise  
The ALVCHR16409 has “bus-hold” which retains the inputs’ last state  
whenever the input bus goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistors.  
APPLICATIONS:  
3.3V High Speed Systems  
3.3V and lower voltage computing systems  
FUNCTIONALBLOCKDIAGRAM  
56  
1
CLK  
PRE  
55  
28  
SELEN  
SEL2  
2
29  
30  
FlonControl  
SEL0  
SEL1  
SEL3  
SEL4  
27  
3
2Ax 1Ax  
CLK  
D
CLK  
D
2Ax  
2Bx  
1Bx  
2Bx  
54  
1B1  
3
3
1Ax  
2Ax  
1Bx  
1Ax  
1Bx  
2Bx  
1Ax  
CLK  
D
CLK  
2Ax  
1Bx  
D
42  
15  
2B1  
2A1  
2Bx  
One of 9 Channels  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
OCTOBER 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4586/-  

与74ALVCHR16409PF8相关器件

型号 品牌 获取价格 描述 数据表
74ALVCHR16409PV IDT

获取价格

SSOP-56, Tube
74ALVCHR16543PA IDT

获取价格

TSSOP-56, Tube
74ALVCHR16543PA8 IDT

获取价格

TSSOP-56, Reel
74ALVCHR16543PF IDT

获取价格

TVSOP-56, Tube
74ALVCHR16543PV8 IDT

获取价格

SSOP-56, Reel
74ALVCHS162830 NXP

获取价格

18-bit to 36-bit address driver with bus hold (3-State)
74ALVCHS162830A TI

获取价格

1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
74ALVCHS162830A_09 TI

获取价格

1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
74ALVCHS162830AGR TI

获取价格

1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
74ALVCHS162830DGB NXP

获取价格

18-bit to 36-bit address driver with bus hold (3-State)