IDT74ALVCH373
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
INDUSTRIALTEMPERATURERANGE
3.3V CMOS OCTAL
IDT74ALVCH373
TRANSPARENT D-TYPE
LATCH WITH 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
FEATURES:
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–
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0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
VCC = 3.3V ±0.3V, Normal Range
This octal transparent D-type latch is built using advanced dual metal
CMOS technology. The ALVCH373 device is particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers, and
workingregisters.While the latch-enable (LE)inputis high,the Qoutputs
followthe data (D)inputs.WhenLEis takenlow,the Qoutputs are latched
atthe logiclevels setupatthe Dinputs.
–
–
–
–
–
–
V
CC
= 2.7V to 3.6V, Extended Range
VCC = 2.5V ±0.2V
CMOS power levels (0.4µW typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SOIC, SSOP, QSOP, and TSSOP packages
Abufferedoutput-enable(OE)inputcanbeusedtoplacetheeightoutputs
ineithera normallogicstate (highorlowlogiclevels)ora high-impedance
state.Inthehigh-impedancestate,theoutputsneitherloadnordrivethebus
lines significantly.The high-impedance state andincreaseddrive provide
the capabilitytodrive bus lines withoutinterface orpullupcomponents.
Drive Features for ALVCH373:
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–
High Output Drivers: ±24mA
Suitable for heavy loads
The ALVCH373 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
APPLICATIONS:
The ALVCH373 has a “bus-hold” which retains the inputs’ last state
wheneverthe inputbus goes toa highimpedance.This prevents floating
inputs andeliminates the needforpull-up/downresistors.
• 3.3V High Speed Systems
• 3.3Vandlowervoltagecomputingsystems
FUNCTIONALBLOCKDIAGRAM
1
OE
11
LE
C1
1D
2
1Q
3
1
D
TO SEVEN OTHER CHANNELS
MARCH1999
INDUSTRIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
DSC-4474/-