Datasheet > 74ALVCH373PY8

74ALVCH373PY8

更新时间： 2024-09-16 19:38:19

品牌	Logo	应用领域
艾迪悌 - IDT		逻辑集成电路
页数	文件大小	规格书
6页	87K
描述
SSOP-20, Reel

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74ALVCH373PY8 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	,	针数：	20
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.91	JESD-609代码：	e0
逻辑集成电路类型：	D LATCH	湿度敏感等级：	1
峰值回流温度（摄氏度）：	240	端子面层：	Tin/Lead (Sn/Pb)
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

74ALVCH373PY8 数据手册

IDT74ALVCH373

3.3VCMOSOCTALTRANSPARENTD-TYPELATCH

INDUSTRIALTEMPERATURERANGE

3.3V CMOS OCTAL

IDT74ALVCH373

TRANSPARENT D-TYPE

LATCH WITH 3-STATE

OUTPUTS AND BUS-HOLD

DESCRIPTION:

FEATURES:

–

0.5 MICRON CMOS Technology

Typical tSK(o) (Output Skew) < 250ps

ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

VCC = 3.3V ±0.3V, Normal Range

This octal transparent D-type latch is built using advanced dual metal

CMOS technology. The ALVCH373 device is particularly suitable for

implementing buffer registers, I/O ports, bidirectional bus drivers, and

workingregisters.While the latch-enable (LE)inputis high,the Qoutputs

followthe data (D)inputs.WhenLEis takenlow,the Qoutputs are latched

atthe logiclevels setupatthe Dinputs.

–

= 2.7V to 3.6V, Extended Range

VCC = 2.5V ±0.2V

CMOS power levels (0.4µW typ. static)

Rail-to-Rail output swing for increased noise margin

Available in SOIC, SSOP, QSOP, and TSSOP packages

Abufferedoutput-enable(OE)inputcanbeusedtoplacetheeightoutputs

ineithera normallogicstate (highorlowlogiclevels)ora high-impedance

state.Inthehigh-impedancestate,theoutputsneitherloadnordrivethebus

lines significantly.The high-impedance state andincreaseddrive provide

the capabilitytodrive bus lines withoutinterface orpullupcomponents.

Drive Features for ALVCH373:

–

High Output Drivers: ±24mA

Suitable for heavy loads

The ALVCH373 has been designed with a ±24mA output driver. This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

APPLICATIONS:

The ALVCH373 has a “bus-hold” which retains the inputs’ last state

wheneverthe inputbus goes toa highimpedance.This prevents floating

inputs andeliminates the needforpull-up/downresistors.

• 3.3V High Speed Systems

• 3.3Vandlowervoltagecomputingsystems

FUNCTIONALBLOCKDIAGRAM

¹D

¹Q

TO SEVEN OTHER CHANNELS

MARCH1999

INDUSTRIAL TEMPERATURE RANGE

1999 Integrated Device Technology, Inc.

DSC-4474/-

12 3 4 5 6

中文翻译

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与74ALVCH373PY8相关器件

型号	品牌	获取价格	描述	数据表
74ALVCH373Q	IDT	获取价格	QSOP-20, Tube
74ALVCH373Q8	IDT	获取价格	QSOP-20, Reel
74ALVCH373SO	IDT	获取价格	SOIC-20, Tube
74ALVCH373SO8	IDT	获取价格	SOIC-20, Reel
74ALVCH374PG	IDT	获取价格	TSSOP-20, Tube
74ALVCH374PY	IDT	获取价格	SSOP-20, Tube
74ALVCH374Q	IDT	获取价格	QSOP-20, Tube
74ALVCH374SO	IDT	获取价格	SOIC-20, Tube
74ALVCHR162245PAG	IDT	获取价格	3.3V CMOS 16-BIT BUS TRANSCIEVER
74ALVCHR162245PAG8	IDT	获取价格	3.3V CMOS 16-BIT BUS TRANSCIEVER

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