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74ALVCH32973ZKER

更新时间： 2024-11-05 22:07:07
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路
页数 文件大小 规格书
13页 264K
描述
16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS

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74ALVCH32973ZKER 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Lifetime Buy零件包装代码：BGA
包装说明：LFBGA, BGA96,6X16,32针数：96
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：7.61Is Samacsys：N
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PBGA-B96
JESD-609代码：e1长度：13.5 mm
逻辑集成电路类型：BUS TRANSCEIVER最大I（ol）：0.024 A
湿度敏感等级：3位数：8
功能数量：2端口数量：2
端子数量：96最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA96,6X16,32
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.06 mA
Prop。Delay @ Nom-Sup：3 ns传播延迟（tpd）：3.3 ns
认证状态：Not Qualified座面最大高度：1.4 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：5.5 mm
Base Number Matches：1

74ALVCH32973ZKER 数据手册

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SN74ALVCH32973  
16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH  
WITH EIGHT INDEPENDENT BUFFERS  
www.ti.com  
SCES436C–APRIL 2003–REVISED SEPTEMBER 2004  
FEATURES  
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
•
Member of the Texas Instruments Widebus+™  
Family  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This device contains eight independent noninverting buffers and a 16-bit noninverting bus transceiver and D-type  
latch designed for 1.65-V to 3.6-V VCC operation.  
The SN74ALVCH32973 is particularly suitable for demultiplexing an address/data bus into a dedicated address  
bus and dedicated data bus. The device is used where there is asynchronous bidirectional communication  
between the A and B data bus, and the address signals are latched and buffered on the Q bus. The  
control-function implementation minimizes external timing requirements.  
This device can be used as one 8-bit buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one  
16-bit transceiver, and one 16-bit latch. It allows data transmission from the A bus to the B bus or from the B bus  
to the A bus, depending on the logic level at the direction-control (DIR) input. The transceiver output-enable  
(TOE) input can be used to disable the transceivers so that the A and B buses effectively are isolated.  
When the latch-enable (LE) input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Q  
outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE) input can be used to place  
the nine Q outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the  
high-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE does not affect  
internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in  
the high-impedance state.  
To ensure the high-impedance state during power up or power down, LOE and TOE should be tied to VCC  
through pullup resistors; the minimum values of the resistors are determined by the current-sinking capability of  
the drivers.  
The eight independent noninverting buffers perform the Boolean function Y = D and are independent of the state  
of DIR, TOE, LE, and LOE.  
The A and B I/Os and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data  
inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCH32973KR  
TOP-SIDE MARKING  
ACH973  
LFBGA - GKE  
LFBGA - ZKE (Pb-free)  
-40°C to 85°C  
Tape and reel  
74ALVCH32973ZKER  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus+ is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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74ALVCH32973ZKER 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH32973KR TI

完全替代

 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS

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