5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> 74ALVCH16835DLG4
74ALVCH16835DLG4 PDF预览

74ALVCH16835DLG4

更新时间： 2024-11-18 05:05:51
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
17页 487K
描述
18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

74ALVCH16835DLG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.55Is Samacsys：N
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：18.415 mm
逻辑集成电路类型：BUS DRIVER湿度敏感等级：1
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：5.5 ns
认证状态：Not Qualified座面最大高度：2.79 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.49 mm
Base Number Matches：1

74ALVCH16835DLG4 数据手册

 浏览型号74ALVCH16835DLG4的Datasheet PDF文件第2页浏览型号74ALVCH16835DLG4的Datasheet PDF文件第3页浏览型号74ALVCH16835DLG4的Datasheet PDF文件第4页浏览型号74ALVCH16835DLG4的Datasheet PDF文件第5页浏览型号74ALVCH16835DLG4的Datasheet PDF文件第6页浏览型号74ALVCH16835DLG4的Datasheet PDF文件第7页 
SN74ALVCH16835  
18-BIT UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES053J–SEPTEMBER 1995–REVISED OCTOBER 2004  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
NC  
NC  
GND  
NC  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Max tpd of 3.6 ns at 3.3 V  
2
3
Y1  
GND  
Y2  
A1  
GND  
A2  
±24-mA Output Drive at 3.3 V  
4
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
5
6
Y3  
A3  
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
7
V
CC  
V
CC  
8
Y4  
Y5  
Y6  
GND  
Y7  
Y8  
A4  
A5  
A6  
GND  
A7  
9
ESD Protection Exceeds JESD 22  
- 2000-V Human-Body Model (A114-A)  
- 200-V Machine Model (A115-A)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
DESCRIPTION/ORDERING INFORMATION  
A8  
Y9  
A9  
This 18-bit universal bus driver is designed for 1.65-V  
to 3.6-V VCC operation.  
Y10  
Y11  
Y12  
GND  
Y13  
Y14  
Y15  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
Data flow from  
A to Y is controlled by the  
output-enable (OE) input. The device operates in the  
transparent mode when the latch-enable (LE) input is  
high. The A data is latched if the clock (CLK) input is  
held at a high or low logic level. If LE is low, the A  
data is stored in the latch/flip-flop on the low-to-high  
transition of CLK. When OE is high, the outputs are in  
the high-impedance state.  
V
CC  
V
CC  
Y16  
Y17  
GND  
Y18  
OE  
A16  
A17  
GND  
A18  
CLK  
GND  
To ensure the high-impedance state during power up  
or power down, OE should be tied to VCC through a  
pullup resistor; the minimum value of the resistor is  
determined by the current-sinking capability of the  
driver.  
LE  
Active bus-hold circuitry holds unused or undriven  
inputs at a valid logic state. Use of pullup or pulldown  
resistors with the bus-hold circuitry is not  
recommended.  
NC − No internal connection  
xxxx  
xxxx  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
Tube  
SN74ALVCH16835DL  
SN74ALVCH16835DLR  
SN74ALVCH16835DGGR  
SN74ALVCH16835DGVR  
SN74ALVCH16835KR  
74ALVCH16835ZQLR  
SSOP - DL  
ALVCH16835  
Tape and reel  
Tape and reel  
Tape and reel  
TSSOP - DGG  
ALVCH16835  
VH835  
-40°C to 85°C  
TVSOP - DGV  
VFBGA - GQL  
Tape and reel  
VH835  
VFBGA - ZQL (Pb-free)  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...17

中文翻译

下载PDF

与74ALVCH16835DLG4相关器件

型号 品牌 获取价格 描述 数据表
74ALVCH16835DLRG4 TI

获取价格

 		18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
74ALVCH16835ZQLR TI

获取价格

 		18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
74ALVCH16841 NXP

获取价格

 		20-bit bus interface D-type latch 3-State
74ALVCH16841DGG NXP

获取价格

 		20-bit bus interface D-type latch 3-State
74ALVCH16841DGG NEXPERIA

获取价格

 		20-bit bus interface D-type latch; 3-stateProduction
74ALVCH16841DGG,11 NXP

获取价格

 		74ALVCH16841 - 20-bit bus interface D-type latch (3-State) TSSOP 56-Pin
74ALVCH16841DGG:11 NXP

获取价格

 		74ALVCH16841 - 20-bit bus interface D-type latch (3-State) TSSOP 56-Pin
74ALVCH16841DGGRE4 TI

获取价格

 		20-Bit Bus-Interface D-Type Latch With 3-State Outputs 56-TSSOP -40 to 85
74ALVCH16841DGGRG4 TI

获取价格

 		ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56
74ALVCH16841DGG-T NXP

获取价格

 		暂无描述

与74ALVCH16835DLG4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证