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74ALVCH162240TX PDF预览

74ALVCH162240TX

更新时间: 2024-11-16 23:24:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 89K
描述
Quad 4-Bit Buffer/Driver

74ALVCH162240TX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:6.10 MM, MO-153, TSSOP-48
针数:48Reach Compliance Code:not_compliant
风险等级:5.92Is Samacsys:N
控制类型:ENABLE LOW系列:ALVC/VCX/A
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:12.5 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.012 A湿度敏感等级:2
位数:4功能数量:4
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:3.3 VProp。Delay @ Nom-Sup:3.8 ns
传播延迟(tpd):7.6 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:6.1 mmBase Number Matches:1

74ALVCH162240TX 数据手册

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November 2001  
Revised November 2001  
74ALVCH162240  
Low Voltage 16-Bit Inverting Buffer/Line Driver  
with Bushold and 26Series Resistors in Outputs  
General Description  
The ALVCH162240 contains sixteen inverting buffers with  
Features  
1.65V to 3.6V VCC supply operation  
3-STATE outputs to be employed as  
a memory and  
3.6V tolerant control inputs and outputs  
address driver, clock driver, or bus oriented transmitter/  
receiver. The device is nibble (4-bit) controlled. Each nibble  
has separate 3-STATE control inputs which can be shorted  
together for full 16-bit operation.  
Bushold on data inputs eliminating the need for external  
pull-up/pull-down resistors  
26series resistors in outputs  
tPD  
The ALVCH162240 data inputs include active bushold cir-  
cuitry, eliminating the need for external pull-up resistors to  
hold unused or floating data inputs at a valid logic level.  
3.8 ns max for 3.0V to 3.6V VCC  
4.3 ns max for 2.3V to 2.7V VCC  
7.6 ns max for 1.65V to 1.95V VCC  
The 74ALVCH162240 is also designed with 26series  
resistors in the outputs. This design reduces line noise in  
applications such as memory address drivers, clock driv-  
ers, and bus transceivers/transmitters.  
Uses patented noise/EMI reduction circuitry  
Latchup conforms to JEDEC JED78  
ESD performance:  
The 74ALVCH162240 is designed for low voltage (1.65V to  
3.6V) VCC applications with output capability up to 3.6V.  
Human body model > 2000V  
The 74ALVCH162240 is fabricated with an advanced  
CMOS technology to achieve high speed operation while  
maintaining low CMOS power dissipation.  
Machine model > 200V  
Ordering Code:  
Order Number Package Number  
Package Descriptions  
74ALVCH162240T  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OEn  
I0I15  
Output Enable Input (Active LOW)  
Bushold Inputs  
O0O15  
Outputs  
© 2001 Fairchild Semiconductor Corporation  
DS500700  
www.fairchildsemi.com  

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