74ALVC16601

更新时间： 2024-11-04 22:39:51

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器
页数	文件大小	规格书
8页	103K
描述
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

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74ALVC16601 数据手册

October 2001

Revised October 2001

74ALVC16601

Low Voltage 18-Bit Universal Bus Transceivers

with 3.6V Tolerant Inputs and Outputs

General Description

The ALVC16601 is an 18-bit universal bus transceiver

which combines D-type latches and D-type flip-flops to

allow data flow in transparent, latched, and clocked modes.

Features

■ 1.65V–3.6V V_CCsupply operation

■ 3.6V tolerant inputs and outputs

■ t_PD(A to B, B to A)

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. The clock can be con-

trolled by the clock-enable (CLKENAB and CLKENBA)

inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is HIGH. When LEAB is

LOW, the A data is latched if CLKAB is held at a HIGH-to-

LOW logic level. If LEAB is LOW, the A bus data is stored

in the latch/flip-flop on the LOW-to-HIGH transition of

CLKAB. When OEAB is LOW, the outputs are active. When

OEAB is HIGH, the outputs are in the high-impedance

state.

3.4 ns max for 3.0V to 3.6V V_CC

4.0 ns max for 2.3V to 2.7V V_CC

7.0 ns max for 1.65V 1.95V V_CC

■ Power-down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■ Uses patented noise/EMI reduction circuitry

■ Latchup conforms to JEDEC JED78

■ ESD performance:

Human body model > 2000V

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, CLKBA and CLKENBA.

Machine model >200V

■ Also packaged in plastic Fine-Pitch Ball Grid Array

The ALVC16601 is designed for low voltage (1.65V to

3.6V) V_CCapplications with I/O capability up to 3.6V.

(FBGA) (Preliminary)

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V_CCthrough a pull-up resistor; the minimum

The ALVC16601 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Order Number

Package Number

Package Description

74ALVC16601GX

(Note 2)

BGA54A

(Preliminary)

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

74ALVC16601MTD

(Note 3)

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Note 2: BGA package available in Tape and Reel only.

Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

DS500682

www.fairchildsemi.com

12 3 4 5 6 7 8

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与74ALVC16601相关器件

型号	品牌	获取价格	描述	数据表
74ALVC16601DGG	ETC	获取价格	18-Bit Bus Transceiver
74ALVC16601DL	ETC	获取价格	18-Bit Bus Transceiver
74ALVC16601DL-T	NXP	获取价格	IC ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, Bus Driver/Trans
74ALVC16601GX	FAIRCHILD	获取价格	Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
74ALVC16601MTD	FAIRCHILD	获取价格	Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
74ALVC16601MTDX	FAIRCHILD	获取价格	18-Bit Bus Transceiver
74ALVC16623DGG	NXP	获取价格	IC ALVC/VCX/A SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver
74ALVC16623DGG-T	NXP	获取价格	IC ALVC/VCX/A SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver
74ALVC16623DL	ETC	获取价格	Dual 8-bit Bus Transceiver
74ALVC16646DGG	NXP	获取价格	IC ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, Bus Driver/T

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