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74ALVC162827 PDF预览

74ALVC162827

更新时间: 2024-09-15 22:56:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
6页 80K
描述
Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26з Series Resistors in the Outputs

74ALVC162827 数据手册

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November 2001  
Revised November 2001  
74ALVC162827  
Low Voltage 20-Bit Buffer/Line Driver  
with 3.6V Tolerant Inputs and Outputs  
and 26Series Resistors in the Outputs  
General Description  
Features  
1.65V to 3.6V VCC supply operation  
The ALVC162827 contains twenty non-inverting buffers  
with 3-STATE outputs to be employed as a memory and  
address driver, clock driver, or bus oriented transmitter/  
receiver. The device is byte controlled. Each byte has NOR  
output enables for maximum control flexibility.  
3.6V tolerant inputs and outputs  
26series resistors in outputs  
tPD  
The 74ALVC162827 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O capability up to 3.6V. The  
3.9 ns max for 3.0V to 3.6V VCC  
4.6 ns max for 2.3V to 2.7V VCC  
8.2 ns max for 1.65V to 1.95V VCC  
ALVC162827 is also designed with 26resistors in the  
outputs.  
Power-off high impedance inputs and outputs  
Supports live insertion and withdrawal (Note 1)  
Uses patented noise/EMI reduction circuitry  
Latchup conforms to JEDEC JED78  
ESD performance:  
The 74ALVC162827 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pull-up resistor; the minimum  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74ALVC162827T  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OEn  
Output Enable Input (Active LOW)  
I0I19  
O0O19  
Inputs  
Outputs  
© 2001 Fairchild Semiconductor Corporation  
DS500698  
www.fairchildsemi.com  

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