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74ALVC162244PAG8 PDF预览

74ALVC162244PAG8

更新时间: 2024-11-22 09:49:55
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 377K
描述
3.3V CMOS 16-Bit Buffer/Driver with 3-State Outputs, TSSOP0/Reel

74ALVC162244PAG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP48,.3,20针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.22
控制类型:ENABLE LOW系列:ALVC/VCX/A
JESD-30 代码:R-PDSO-G48JESD-609代码:e3
长度:12.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.012 A
湿度敏感等级:1位数:4
功能数量:4端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:4.2 ns
传播延迟(tpd):4.9 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:6.1 mm
Base Number Matches:1

74ALVC162244PAG8 数据手册

 浏览型号74ALVC162244PAG8的Datasheet PDF文件第2页浏览型号74ALVC162244PAG8的Datasheet PDF文件第3页浏览型号74ALVC162244PAG8的Datasheet PDF文件第4页浏览型号74ALVC162244PAG8的Datasheet PDF文件第5页浏览型号74ALVC162244PAG8的Datasheet PDF文件第6页 
3.3V CMOS 16-BIT  
IDT74ALVC162244  
BUFFER/DRIVER WITH  
3-STATE OUTPUTS  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
This 16-bit buffer/driver is built using advanced dual metal CMOS  
technology. The ALVC162244 is designed specifically to improve the  
performance and density of 3-state memory address drivers, clock  
drivers,andbus-orientedreceivers andtransmitters.The device canbe  
usedasfour4-bitbuffers,two8-bitbuffers,orone16-bitbuffer.Itprovides  
trueoutputs andsymmetricalactive-lowoutput-enable(OE)inputs.  
The ALVC162244 has series resistors in the device output structure  
whichwillsignificantlyreduce line noise whenusedwithlightloads.This  
driver has been designed to drive ±12mA at the designated threshold  
levels.  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
• CMOS power levels (0.4μ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
Available in TSSOP package  
DRIVE FEATURES:  
• Balanced Output Drivers: ±12mA  
Low switching noise  
APPLICATIONS:  
• 3.3V high speed systems  
• 3.3V and lower voltage computing systems  
FUNCTIONALBLOCKDIAGRAM  
25  
1
1OE  
3OE  
13  
36  
47  
2
1A1  
3A1  
1Y1  
1Y2  
1Y3  
1Y4  
3Y1  
3Y2  
3Y3  
3Y4  
3
5
35  
33  
32  
46  
44  
14  
16  
1A2  
1A3  
3A2  
3A3  
3A4  
43  
48  
6
17  
1A4  
24  
2OE  
2A1  
4OE  
4A1  
30  
29  
27  
26  
41  
40  
38  
8
9
19  
2Y1  
2Y2  
2Y3  
2Y4  
4Y1  
4Y2  
4Y3  
4Y4  
20  
22  
23  
2A2  
2A3  
4A2  
4A3  
11  
12  
37  
2A4  
4A4  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
OCTOBER 2008  
1
© 2006 Integrated Device Technology, Inc.  
DSC-4560/5  

74ALVC162244PAG8 替代型号

型号 品牌 替代类型 描述 数据表
74ALVC162244TX FAIRCHILD

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Quad 4-Bit Buffer/Driver
74ALVC162244T FAIRCHILD

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Low Voltage 16-Bit Buffer/Line Driver with 3.

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