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74AHCT2G32DP PDF预览

74AHCT2G32DP

更新时间: 2024-11-07 22:11:47
品牌 Logo 应用领域
恩智浦 - NXP 逻辑集成电路光电二极管
页数 文件大小 规格书
16页 83K
描述
Dual 2-input OR gate

74AHCT2G32DP 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOIC
包装说明:3 MM, PLASTIC, SOT505-2, TSSOP-8针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.43系列:AHCT/VHCT/VT
JESD-30 代码:S-PDSO-G8JESD-609代码:e4
长度:3 mm负载电容(CL):50 pF
逻辑集成电路类型:OR GATE最大I(ol):0.008 A
湿度敏感等级:1功能数量:2
输入次数:2端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.16封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:10 ns
传播延迟(tpd):10 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3 mmBase Number Matches:1

74AHCT2G32DP 数据手册

 浏览型号74AHCT2G32DP的Datasheet PDF文件第2页浏览型号74AHCT2G32DP的Datasheet PDF文件第3页浏览型号74AHCT2G32DP的Datasheet PDF文件第4页浏览型号74AHCT2G32DP的Datasheet PDF文件第5页浏览型号74AHCT2G32DP的Datasheet PDF文件第6页浏览型号74AHCT2G32DP的Datasheet PDF文件第7页 
74AHC2G32; 74AHCT2G32  
Dual 2-input OR gate  
Rev. 01 — 23 February 2004  
Product data sheet  
1. General description  
The 74AHC2G/AHCT2G32 is a high-speed Si-gate CMOS device. This device provides  
two 2-input OR gates.  
2. Features  
Symmetrical output impedance  
High noise immunity  
ESD protection:  
HBM EIA/JESD22-A114-A exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
CDM EIA/JESD22-C101 exceeds 1000 V.  
Low power dissipation  
Balanced propagation delays  
SOT505-2 and SOT765-1 package  
Specified from 40 °C to +85 °C and 40 °C to +125 °C.  
3. Quick reference data  
Table 1:  
Quick reference data  
GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Type 74AHC2G  
tPHL, tPLH  
propagation delay CL = 15 pF;  
-
3.2  
5.5  
ns  
nA and nB to nY  
VCC = 5 V  
CI  
input capacitance  
-
-
1.5  
16  
10  
-
pF  
pF  
[1] [2]  
CPD  
power dissipation CL = 50 pF;  
capacitance fi = 1 MHz  
Type 74AHCT2G  
tPHL, tPLH  
propagation delay CL = 15 pF;  
-
3.3  
6.9  
ns  
nA and nB to nY  
VCC = 5 V  
CI  
input capacitance  
-
-
1.5  
17  
10  
-
pF  
pF  
[1] [2]  
CPD  
power dissipation CL = 50 pF;  
capacitance fi = 1 MHz  
[1] CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  

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