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74AHCT2G32 PDF预览

74AHCT2G32

更新时间: 2024-11-23 22:11:47
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
16页 83K
描述
Dual 2-input OR gate

74AHCT2G32 数据手册

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74AHC2G32; 74AHCT2G32  
Dual 2-input OR gate  
Rev. 01 — 23 February 2004  
Product data sheet  
1. General description  
The 74AHC2G/AHCT2G32 is a high-speed Si-gate CMOS device. This device provides  
two 2-input OR gates.  
2. Features  
Symmetrical output impedance  
High noise immunity  
ESD protection:  
HBM EIA/JESD22-A114-A exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
CDM EIA/JESD22-C101 exceeds 1000 V.  
Low power dissipation  
Balanced propagation delays  
SOT505-2 and SOT765-1 package  
Specified from 40 °C to +85 °C and 40 °C to +125 °C.  
3. Quick reference data  
Table 1:  
Quick reference data  
GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Type 74AHC2G  
tPHL, tPLH  
propagation delay CL = 15 pF;  
-
3.2  
5.5  
ns  
nA and nB to nY  
VCC = 5 V  
CI  
input capacitance  
-
-
1.5  
16  
10  
-
pF  
pF  
[1] [2]  
CPD  
power dissipation CL = 50 pF;  
capacitance fi = 1 MHz  
Type 74AHCT2G  
tPHL, tPLH  
propagation delay CL = 15 pF;  
-
3.3  
6.9  
ns  
nA and nB to nY  
VCC = 5 V  
CI  
input capacitance  
-
-
1.5  
17  
10  
-
pF  
pF  
[1] [2]  
CPD  
power dissipation CL = 50 pF;  
capacitance fi = 1 MHz  
[1] CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  

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