74AHCT2G241

更新时间： 2024-09-17 22:40:23

品牌	Logo	应用领域
恩智浦 - NXP		驱动器
页数	文件大小	规格书
19页	102K
描述
Dual buffer/line driver; 3-state

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数据手册

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74AHCT2G241 数据手册

74AHC2G241; 74AHCT2G241

Dual buffer/line driver; 3-state

Rev. 01 — 10 March 2004

Product data sheet

1. General description

The 74AHC2G241; 74AHCT2G241 is a high-speed Si-gate CMOS device.

The 74AHC2G241; 74AHCT2G241 is a dual non-inverting buffer/line driver with 3-state

outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A

HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW

level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.

Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise

and fall times.

2. Features

■ Symmetrical output impedance

■ High noise immunity

■ ESD protection:

◆ HBM EIA/JESD22-A114-A exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V

◆ CDM EIA/JESD22-C101 exceeds 1000 V.

■ Low power dissipation

■ Balanced propagation delays

■ SOT505-2 and SOT765-1 package

■ Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C.

3. Quick reference data

Table 1:

Quick reference data

GND = 0 V; T_amb= 25 °C; t_r= t_f≤ 3.0 ns.

Symbol Parameter

Type 74AHC2G241

Conditions

Min Typ Max Unit

t_PHL, t_PLHpropagation delay nA to nY C_L= 15 pF; V_CC= 5 V

3.4

3.6

4.1

4.3

1.5

5.5

5.1

5.6

6.8

t_PZH, t_PZLenable time1OE to 1Y

enable time 2OE to 2Y

C_L= 15 pF; V_CC= 5 V

t_PHZ, t_PLZdisable time1OE to 1Y

disable time 2OE to 2Y

C_I

input capacitance

[1] [2]

C_PD

power dissipation

capacitance

C_L= 50 pF; f = 1 MHz

12 3 4 5 6 7...19

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