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74AHCT257D PDF预览

74AHCT257D

更新时间: 2024-11-25 11:11:07
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
16页 596K
描述
Quad 2-input multiplexer; 3-stateProduction

74AHCT257D 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:3.90 MM, PLASTIC, MS-012, SOT-109-1 SOP-16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.15
Is Samacsys:N系列:AHCT/VHCT/VT
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm逻辑集成电路类型:MULTIPLEXER
湿度敏感等级:1功能数量:4
输入次数:2输出次数:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):13.5 ns认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

74AHCT257D 数据手册

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74AHC257; 74AHCT257  
Quad 2-input multiplexer; 3-state  
Rev. 02 — 9 May 2008  
Product data sheet  
1. General description  
The 74AHC257; 74AHCT257 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
No. 7-A.  
The 74AHC257; 74AHCT257 has four identical 2-input multiplexers with 3-state outputs,  
which select 4 bits of data from two sources and are controlled by a common data select  
input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and  
the data inputs from source 1 (1I1 to 4I1) are selected when input S is HIGH. Data  
appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs.  
The 74AHC257; 74AHCT257 is the logic implementation of a 4-pole 2-position switch,  
where the position of the switch is determined by the logic levels applied to input S. The  
outputs are forced to a high-impedance OFF-state when OE is HIGH.  
The logic equations for the outputs are:  
1Y = OE × (1I1 × S + 1I0 × S)  
2Y = OE × (2I1 × S + 2I0 × S)  
3Y = OE × (3I1 × S + 3I0 × S)  
4Y = OE × (4I1 × S + 4I0 × S)  
The 74AHC257; 74AHCT257 is identical to the 74AHC258; 74AHCT258, but has  
non-inverting (true) outputs.  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger actions  
I Non-inverting data path  
I Inputs accept voltages higher than VCC  
I Input levels:  
N For 74AHC257: CMOS level  
N For 74AHCT257: TTL level  
I ESD protection:  
N HBM EIA/JESD22-A114E exceeds 2000 V  
N MM EIA/JESD22-A115-A exceeds 200 V  
N CDM EIA/JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  

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