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74AHCT1G126DCKTE4 PDF预览

74AHCT1G126DCKTE4

更新时间: 2024-11-20 12:34:39
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
13页 819K
描述
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

74AHCT1G126DCKTE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:TSSOP, TSSOP5/6,.08针数:5
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.26控制类型:ENABLE HIGH
系列:AHCT/VHCT/VTJESD-30 代码:R-PDSO-G5
JESD-609代码:e4长度:2 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:1功能数量:1
端口数量:2端子数量:5
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP5/6,.08封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:8.5 ns传播延迟(tpd):8.5 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.25 mmBase Number Matches:1

74AHCT1G126DCKTE4 数据手册

 浏览型号74AHCT1G126DCKTE4的Datasheet PDF文件第2页浏览型号74AHCT1G126DCKTE4的Datasheet PDF文件第3页浏览型号74AHCT1G126DCKTE4的Datasheet PDF文件第4页浏览型号74AHCT1G126DCKTE4的Datasheet PDF文件第5页浏览型号74AHCT1G126DCKTE4的Datasheet PDF文件第6页浏览型号74AHCT1G126DCKTE4的Datasheet PDF文件第7页 
SN74AHCT1G126  
SINGLE BUS BUFFER GATE  
WITH 3-STATE OUTPUT  
SCLS380I – AUGUST 1997 – REVISED JANUARY 2003  
DBV OR DCK PACKAGE  
(TOP VIEW)  
Operating Range of 4.5 V to 5.5 V  
Max t of 6 ns at 5 V  
pd  
Low Power Consumption, 10-µA Max I  
±8-mA Output Drive at 5 V  
1
2
3
5
4
CC  
OE  
A
GND  
V
Y
CC  
Inputs Are TTL-Voltage Compatible  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
description/ordering information  
The SN74AHCT1G126 is a single bus buffer gate/line driver with 3-state output. The output is disabled when  
the output-enable (OE) input is low. When OE is high, true data is passed from the A input to the Y output.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the  
driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Reel of 3000  
Reel of 250  
Reel of 3000  
SN74AHCT1G126DBVR  
SN74AHCT1G126DBVT  
SN74AHCT1G126DCKR  
SOT (SOT-23) – DBV  
B26_  
–40°C to 85°C  
SOT (SC-70) – DCK  
BN_  
Reel of 250  
SN74AHCT1G126DCKT  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
The actual top-side marking has one additional character that designates the assembly/test site.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
H
H
L
H
L
X
Z
logic diagram (positive logic)  
1
2
OE  
A
4
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

74AHCT1G126DCKTE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHCT1G126DCKT TI

完全替代

Single Bus Buffer Gate With 3-State Output 5-SC70 -40 to 125
SN74AHCT1G126DCKR TI

完全替代

暂无描述
74AHCT1G126DCKRE4 TI

完全替代

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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