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74AHCT1G125DCKTG4 PDF预览

74AHCT1G125DCKTG4

更新时间: 2024-11-25 08:03:03
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
13页 574K
描述
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

74AHCT1G125DCKTG4 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SC-70, 5 PIN针数:5
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:1.34
Is Samacsys:N控制类型:ENABLE LOW
计数方向:UNIDIRECTIONAL系列:AHCT/VHCT/VT
JESD-30 代码:R-PDSO-G5JESD-609代码:e4
长度:2 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
湿度敏感等级:1位数:1
功能数量:1端口数量:2
端子数量:5最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP5/6,.08
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):0.01 mA
Prop。Delay @ Nom-Sup:8.5 ns传播延迟(tpd):8.5 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.25 mmBase Number Matches:1

74AHCT1G125DCKTG4 数据手册

 浏览型号74AHCT1G125DCKTG4的Datasheet PDF文件第2页浏览型号74AHCT1G125DCKTG4的Datasheet PDF文件第3页浏览型号74AHCT1G125DCKTG4的Datasheet PDF文件第4页浏览型号74AHCT1G125DCKTG4的Datasheet PDF文件第5页浏览型号74AHCT1G125DCKTG4的Datasheet PDF文件第6页浏览型号74AHCT1G125DCKTG4的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢉ ꢈꢊꢋ  
ꢀꢌ ꢁꢉ ꢍ ꢎ ꢏꢐꢀ ꢏꢐꢑ ꢑ ꢎ ꢒ ꢉ ꢄꢇꢎ  
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SCLS378L − AUGUST 1997 − REVISED JUNE 2005  
D
D
D
D
Operating Range of 4.5 V to 5.5 V  
D
D
Inputs Are TTL-Voltage Compatible  
Max t of 6 ns at 5 V  
pd  
Low Power Consumption, 10-µA Max I  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
CC  
8-mA Output Drive at 5 V  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
1
2
3
5
OE  
A
V
Y
CC  
1
2
3
5
OE  
A
V
Y
OE  
A
V
Y
1
2
3
5
CC  
CC  
4
GND  
4
GND  
4
GND  
See mechanical drawings for dimensions.  
description/ordering information  
The SN74AHCT1G125 is a single bus buffer gate/line driver with 3-state output. The output is disabled when  
the output-enable (OE) input is high. When OE is low, true data is passed from the A input to the Y output.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Reel of 3000  
Reel of 250  
Reel of 3000  
Reel of 250  
Reel of 4000  
SN74AHCT1G125DBVR  
SN74AHCT1G125DBVT  
SN74AHCT1G125DCKR  
SN74AHCT1G125DCKT  
SN74AHCT1G125DRLR  
SOT (SOT-23) − DBV  
B25_  
−40°C to 85°C  
SOT (SC-70) − DCK  
BM_  
BM_  
SOT (SOT-553) − DRL  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
The actual top-side marking has one additional character that designates the assembly/test site.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
logic diagram (positive logic)  
1
2
OE  
A
4
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢇꢤ  
Copyright 2005, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

74AHCT1G125DCKTG4 替代型号

型号 品牌 替代类型 描述 数据表
74AHCT1G125DCKTE4 TI

完全替代

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
74AHCT1G125DCKRG4 TI

完全替代

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AHCT1G125DCKR TI

类似代替

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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