Datasheet > 74AHCT132-Q100

74AHCT132-Q100

更新时间： 2024-11-21 00:58:27

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
18页	744K
描述
Quad 2-input NAND Schmitt trigger

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74AHCT132-Q100 数据手册

74AHC132-Q100; 74AHCT132-Q100

Quad 2-input NAND Schmitt trigger

Rev. 1 — 8 November 2013

Product data sheet

1. General description

The 74AHC132-Q100; 74AHCT132-Q100 is a high-speed Si-gate CMOS device and is

pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with

JEDEC standard No. 7-A.

The 74AHC132-Q100; 74AHCT132-Q100 contains four 2-input NAND gates which accept

standard input signals. They can transform slowly changing input signals into sharply

defined, jitter free output signals. The gate switches at different points for positive-going

and negative-going signals. The difference between the positive voltage V_T+and the

negative V_Tis defined as the hysteresis voltage V_H.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Balanced propagation delays

 Inputs accept voltages higher than V_CC

 Input levels:

 For 74AHC132-Q100: CMOS level

 For 74AHCT132-Q100: TTL level

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM EIA/JESD22-A115-A exceeds 200 V

 Multiple package options

12 3 4 5 6 7...18

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