Datasheet > 74AHCT08PW112

74AHCT08PW112

更新时间： 2024-11-06 12:35:11

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
14页	91K
描述
Quad 2-input AND gate Rev. 03 â 14 November 2007

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74AHCT08PW112 数据手册

74AHC08; 74AHCT08

Quad 2-input AND gate

Rev. 03 — 14 November 2007

Product data sheet

1. General description

The 74AHC08; 74AHCT08 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC

standard JESD7-A.

The 74AHC08; 74AHCT08 provides the quad 2-input AND function.

2. Features

■ Balanced propagation delays

■ All inputs have a Schmitt-trigger action

■ Inputs accepts voltages higher than V_CC

■ For 74AHC08 only: operates with CMOS input levels

■ For 74AHCT08 only: operates with TTL input levels

■ ESD protection:

◆ HBM JESD22-A114E exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

◆ CDM JESD22-C101C exceeds 1000 V

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74AHC08D

−40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74AHCT08D

74AHC08PW

74AHCT08PW

74AHC08BQ

74AHCT08BQ

TSSOP14

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

SOT762-1

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

12 3 4 5 6 7...14

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