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74AHC3GU04DP-G

更新时间： 2024-11-05 13:04:55

品牌	Logo	应用领域
恩智浦 - NXP		栅
页数	文件大小	规格书
17页	95K
描述
Inverter - Description: Triple Hex Inverter (Unbuffered) ; Logic switching levels: CMOS ; Number of pins: 8 ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.5@5V ns; Voltage: 2.0-5.5 V

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74AHC3GU04DP-G 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否无铅：	含铅
是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	unknown	风险等级：	5.74
Base Number Matches：	1

74AHC3GU04DP-G 数据手册

74AHC3GU04

Inverter

Rev. 01 — 5 March 2004

Product data sheet

1. General description

The 74AHC3GU04 is a high-speed Si-gate CMOS device. This device provides the

inverting single stage function.

2. Features

■ Symmetrical output impedance

■ High noise immunity

■ ESD protection:

◆ HBM EIA/JESD22-A114-A exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V

◆ CDM EIA/JESD22-C101 exceeds 1000 V.

■ Low power dissipation

■ Balanced propagation delays

■ SOT505-2 and SOT765-1 package

■ Output capability ±8 mA drive

■ Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C.

3. Quick reference data

Table 1:

Quick reference data

GND = 0 V; T_amb= 25 °C; t_r= t_f≤ 3.0 ns.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_PHL, t_PLH

propagation delay nA to nY V_CC= 5 V;

C_L= 15 pF

2.5

5.5

C_I

input capacitance

3.0

[1]

[2]

C_PD

power dissipation

capacitance

[1] C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in Volts;

N = total load switching outputs;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

[2] The condition is V_I= GND to V_CC

12 3 4 5 6 7...17

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