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74AHC3GU04DP-G PDF预览

74AHC3GU04DP-G

更新时间: 2024-02-15 19:46:37
品牌 Logo 应用领域
恩智浦 - NXP
页数 文件大小 规格书
17页 95K
描述
Inverter - Description: Triple Hex Inverter (Unbuffered) ; Logic switching levels: CMOS ; Number of pins: 8 ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.5@5V ns; Voltage: 2.0-5.5 V

74AHC3GU04DP-G 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否无铅: 含铅
是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:unknown风险等级:5.74
Base Number Matches:1

74AHC3GU04DP-G 数据手册

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74AHC3GU04  
Inverter  
Rev. 01 — 5 March 2004  
Product data sheet  
1. General description  
The 74AHC3GU04 is a high-speed Si-gate CMOS device. This device provides the  
inverting single stage function.  
2. Features  
Symmetrical output impedance  
High noise immunity  
ESD protection:  
HBM EIA/JESD22-A114-A exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
CDM EIA/JESD22-C101 exceeds 1000 V.  
Low power dissipation  
Balanced propagation delays  
SOT505-2 and SOT765-1 package  
Output capability ±8 mA drive  
Specified from 40 °C to +85 °C and from 40 °C to +125 °C.  
3. Quick reference data  
Table 1:  
Quick reference data  
GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
tPHL, tPLH  
propagation delay nA to nY VCC = 5 V;  
CL = 15 pF  
-
2.5  
5.5  
ns  
CI  
input capacitance  
-
-
3.0  
4
10  
-
pF  
pF  
[1]  
[2]  
CPD  
power dissipation  
capacitance  
[1] CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in Volts;  
N = total load switching outputs;  
Σ(CL × VCC2 × fo) = sum of the outputs.  
[2] The condition is VI = GND to VCC  
.

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