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74AHC373D PDF预览

74AHC373D

更新时间: 2024-09-25 11:11:07
品牌 Logo 应用领域
安世 - NEXPERIA 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
13页 227K
描述
Octal D-type transparant latch; 3-stateProduction

74AHC373D 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SO-20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.28
Is Samacsys:N系列:AHC
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:12.8 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):18.5 ns认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmBase Number Matches:1

74AHC373D 数据手册

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74AHC373  
Octal D-type transparant latch; 3-state  
Rev. 4 — 5 March 2019  
Product data sheet  
1. General description  
The 74AHC373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power  
Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.  
The 74AHC373 consists of eight D-type transparent latches featuring separate D-type inputs for  
each latch and 3-state true outputs for bus oriented applications. A latch enable input (LE) and an  
output enable input (OE) are common to all latches.  
When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are  
transparent, i.e. a latch output will change state each time its corresponding Dn input changes.  
When pin LE is LOW, the latches store the information that is present at the Dn inputs, after a  
set-up time preceding the HIGH-to-LOW transition of LE.  
When pin OE is LOW, the contents of the 8 latches are available at the outputs. When pin OE is  
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect  
the state of the latches.  
The 74AHC373 is functionally identical to the 74AHC573; 74AHCT573, but has a different pin  
arrangement.  
2. Features and benefits  
Balanced propagation delays  
All inputs have a Schmitt-trigger action  
Common 3-state output enable input  
Inputs accepts voltages higher than VCC  
Functionally identical to the 74AHC573; 74AHCT573  
Input levels at CMOS input level  
ESD protection:  
HBM EIA/JESD22-A114E exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
CDM EIA/JESD22-C101C exceeds 1000 V  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range  
-40 °C to +125 °C  
Name  
Description  
Version  
74AHC373D  
SO20  
plastic small outline package; 20 leads;  
body width 7.5 mm  
SOT163-1  
74AHC373PW  
-40 °C to +125 °C  
TSSOP20  
plastic thin shrink small outline package;  
20 leads; body width 4.4 mm  
SOT360-1  
 
 
 

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