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Datasheet > 74AHC157PW,118
74AHC157PW,118 PDF预览

74AHC157PW,118

更新时间： 2024-01-31 21:55:12
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
16页 86K
描述
74AHC(T)157 - Quad 2-input multiplexer TSSOP 16-Pin

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74AHC157PW,118 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：TSSOP包装说明：TSSOP,
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：0.62
系列：AHC/VHC/H/U/VJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
逻辑集成电路类型：MULTIPLEXER湿度敏感等级：1
功能数量：4输入次数：2
输出次数：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
传播延迟（tpd）：21.5 ns认证状态：Not Qualified
座面最大高度：1.1 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mmBase Number Matches：1

74AHC157PW,118 数据手册

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74AHC157; 74AHCT157  
Quad 2-input multiplexer  
Rev. 02 — 9 November 2007  
Product data sheet  
1. General description  
The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with  
Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC  
standard no. 7A.  
The 74AHC/AHCT157 are quad 2-input multiplexer which select 4 bits of data from two  
sources under the control of a common data select input (S). The enable input (E) is  
active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of  
all other input conditions.  
Moving the data from two groups of registers to four common output buses is a common  
use of the 74AHC/AHCT157. The state of the common data select input (S) determines  
the particular register from which the data comes. It can also be used as function  
generator. The device is useful for implementing highly irregular logic by generating any  
four of the 16 different functions of two variables with one variable common. The  
74AHC/AHCT157 is logic implementation of a 4-pole, 2-position switch, where the  
position of the switch is determine by the logic levels applied to S.  
The logic equations are:  
1Y = E × (1I1 × S + 1I0 × S)  
2Y = E × (2I1 × S + 2I0 × S)  
3Y = E × (3I1 × S + 3I0 × S)  
4Y = E × (4I1 × S + 4I0 × S)  
The 74AHC/AHCT157 is identical to the 74AHC/AHCT158 but has non-inverting (true)  
outputs.  
2. Features  
■ Balanced propagation delays  
■ All inputs have a Schmitt-trigger action  
■ Inputs accepts voltages higher than VCC  
■ Multiple input enable for easy expansion  
■ Ideal for memory chip select decoding  
■ For 74AHC157 only: operates with CMOS input levels  
■ For 74AHCT157 only: operates with TTL input levels  
■ ESD protection:  
◆ HBM JESD22-A114E exceeds 2000 V  
◆ MM JESD22-A115-A exceeds 200 V  
◆ CDM JESD22-C101C exceeds 1000 V  
 
 
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