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74AHC126BQ PDF预览

74AHC126BQ

更新时间: 2024-11-04 08:02:55
品牌 Logo 应用领域
恩智浦 - NXP 总线驱动器总线收发器逻辑集成电路
页数 文件大小 规格书
15页 92K
描述
Quad buffer/line driver; 3-state

74AHC126BQ 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFN包装说明:HVQCCN,
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.72
Is Samacsys:N系列:AHC/VHC/H/U/V
JESD-30 代码:R-PQCC-N14JESD-609代码:e4
长度:3 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):14.5 ns认证状态:Not Qualified
座面最大高度:1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:2.5 mmBase Number Matches:1

74AHC126BQ 数据手册

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74AHC126; 74AHCT126  
Quad buffer/line driver; 3-state  
Rev. 04 — 12 August 2009  
Product data sheet  
1. General description  
The 74AHC126; 74AHCT126 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
No. 7-A.  
The 74AHC126; 74AHCT126 provides four non-inverting buffer/line drivers with 3-state  
outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE).  
A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state.  
The 74AHC126; 74AHCT126 is identical to the 74AHC125; 74AHCT125 but has active  
HIGH output enable inputs.  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger action  
I Inputs accept voltages higher than VCC  
I Input levels:  
N For 74AHC126: CMOS level  
N For 74AHCT126: TTL level  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
N CDM JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  

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