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74ACTQ843CW PDF预览

74ACTQ843CW

更新时间: 2024-11-02 13:04:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
8页 71K
描述
Bus Driver, ACT Series, 1-Func, 9-Bit, True Output, CMOS, DIE

74ACTQ843CW 技术参数

生命周期:Obsolete零件包装代码:DIE
包装说明:DIE,针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.74Is Samacsys:N
系列:ACTJESD-30 代码:R-XUUC-N24
逻辑集成电路类型:BUS DRIVER位数:9
功能数量:1端口数量:2
端子数量:24输出特性:3-STATE
输出极性:TRUE封装主体材料:UNSPECIFIED
封装代码:DIE封装形状:RECTANGULAR
封装形式:UNCASED CHIP传播延迟(tpd):9 ns
认证状态:Not Qualified最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
端子形式:NO LEAD端子位置:UPPER
Base Number Matches:1

74ACTQ843CW 数据手册

 浏览型号74ACTQ843CW的Datasheet PDF文件第2页浏览型号74ACTQ843CW的Datasheet PDF文件第3页浏览型号74ACTQ843CW的Datasheet PDF文件第4页浏览型号74ACTQ843CW的Datasheet PDF文件第5页浏览型号74ACTQ843CW的Datasheet PDF文件第6页浏览型号74ACTQ843CW的Datasheet PDF文件第7页 
March 1990  
Revised December 1998  
74ACTQ843  
Quiet Series 9-Bit Transparent Latch  
with 3-STATE Outputs  
General Description  
Features  
Guaranteed simultaneous switching noise level and  
The ACTQ843 bus interface latch is designed to eliminate  
the extra packages required to buffer existing latches and  
provide extra data width for wider address/data paths. The  
ACTQ843 utilizes Fairchild FACT Quiet Series technol-  
ogy to guarantee quiet output switching and improved  
dynamic threshold performance. FACT Quiet Series fea-  
tures GTO output control and undershoot corrector in  
addition to a split ground bus for superior performance.  
dynamic threshold performance  
Guaranteed pin-to-pin skew AC performance  
Inputs and outputs on opposite sides of package for  
easy interface with microprocessors  
Improved latch-up immunity  
Outputs source/sink 24 mA  
ACTQ843 has TTL-compatible inputs  
Functionally and pin-compatible to AMD’s AM29843  
3-STATE outputs for bus interfacing  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACTQ843SC  
M24B  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide  
74ACTQ843SPC  
N24C  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
Pin Assignment for DIP and SOIC  
Pin Descriptions  
Pin Names  
Description  
Data Inputs  
D0–D8  
O0–O8  
OE  
Data Outputs  
Output Enable  
Latch Enable  
Clear  
LE  
CLR  
PRE  
Preset  
FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010689.prf  
www.fairchildsemi.com  

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