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74ACTQ374PCX PDF预览

74ACTQ374PCX

更新时间: 2024-12-01 00:01:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
11页 108K
描述
Quiet Series⑩ Octal D-Type Flip-Flop with 3-STATE Outputs

74ACTQ374PCX 数据手册

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July 1989  
Revised November 1999  
74ACQ374 74ACTQ374  
Quiet Series Octal D-Type Flip-Flop  
with 3-STATE Outputs  
General Description  
Features  
ICC and IOZ reduced by 50%  
The ACQ/ACTQ374 is a high-speed, low-power octal D-  
type flip-flop featuring separate D-type inputs for each flip-  
flop and 3-STATE outputs for bus-oriented applications. A  
buffered Clock (CP) and Output Enable (OE) are common  
to all flip-flops.  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Guaranteed pin-to-pin skew AC performance  
Improved latch-up immunity  
The ACQ/ACTQ374 utilizes FACT Quiet Series technol-  
ogy to guarantee quiet output switching and improve  
dynamic threshold performance. FACT Quiet Series fea-  
tures GTO output control and undershoot corrector in  
addition to a split ground bus for superior performance.  
Buffered positive edge-triggered clock  
3-STATE outputs drive bus lines or buffer memory  
address registers  
Outputs source/sink 24 mA  
Faster prop delays than the standard AC/ACT374  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACQ374SC  
74ACQ374SJ  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74ACQ374PC  
74ACTQ374SC  
74ACTQ374SJ  
74ACTQ374QSC  
74ACTQ374PC  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M20B  
M20D  
MQA20  
N20A  
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
D0D7  
CP  
Description  
Data Inputs  
Clock Pulse Input  
OE  
3-STATE Output Enable Input  
3-STATE Outputs  
O0O7  
FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010238  
www.fairchildsemi.com  

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