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74ACTQ240PC PDF预览

74ACTQ240PC

更新时间: 2024-11-18 00:01:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路
页数 文件大小 规格书
11页 103K
描述
Quiet Series. Octal Buffer/Line Driver with 3-STATE Outputs

74ACTQ240PC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.13
Is Samacsys:N控制类型:ENABLE LOW
系列:ACTJESD-30 代码:S-PQCC-J20
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:DIP20,.3封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:7.5 ns
传播延迟(tpd):7.5 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.89 mmBase Number Matches:1

74ACTQ240PC 数据手册

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July 1989  
Revised October 2000  
74ACQ240 74ACTQ240  
Quiet Series Octal Buffer/Line Driver  
with 3-STATE Outputs  
General Description  
Features  
ICC and IOZ reduced by 50%  
The ACQ/ACTQ240 is an inverting octal buffer and line  
driver designed to be employed as a memory address  
driver, clock driver and bus oriented transmitter or receiver  
which provides improved PC board density. The ACQ/  
ACTQ utilizes Fairchild’s Quiet Series technology to  
guarantee quiet output switching and improve dynamic  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Guaranteed pin-to-pin skew AC performance  
Improved latch-up immunity  
threshold performance. FACT Quiet Series  
features  
Inverting 3-STATE outputs drive bus lines or buffer  
GTO output control and undershoot corrector in addition  
to a split ground bus for superior performance.  
memory address registers  
Outputs source/sink 24 mA  
Faster prop delays than the standard ACT240  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACQ240SC  
74ACQ240SJ  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74ACQ240PC  
74ACTQ240SC  
74ACTQ240SJ  
74ACTQ240QSC  
74ACTQ240PC  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M20B  
M20D  
MQA20  
N20A  
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
OE1, OE2  
Description  
3-STATE Output Enable Inputs  
I0I7  
Inputs  
O0O7  
Outputs  
FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 2000 Fairchild Semiconductor Corporation  
DS010234  
www.fairchildsemi.com  

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