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74ACTQ18823CW PDF预览

74ACTQ18823CW

更新时间: 2024-11-17 13:04:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
9页 93K
描述
Bus Driver, ACT Series, 2-Func, 9-Bit, True Output, CMOS, DIE

74ACTQ18823CW 技术参数

生命周期:Obsolete零件包装代码:DIE
包装说明:DIE,针数:56
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.74系列:ACT
JESD-30 代码:R-XUUC-N56逻辑集成电路类型:BUS DRIVER
位数:9功能数量:2
端口数量:2端子数量:56
输出特性:3-STATE输出极性:TRUE
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:RECTANGULAR封装形式:UNCASED CHIP
传播延迟(tpd):9 ns认证状态:Not Qualified
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS端子形式:NO LEAD
端子位置:UPPERBase Number Matches:1

74ACTQ18823CW 数据手册

 浏览型号74ACTQ18823CW的Datasheet PDF文件第2页浏览型号74ACTQ18823CW的Datasheet PDF文件第3页浏览型号74ACTQ18823CW的Datasheet PDF文件第4页浏览型号74ACTQ18823CW的Datasheet PDF文件第5页浏览型号74ACTQ18823CW的Datasheet PDF文件第6页浏览型号74ACTQ18823CW的Datasheet PDF文件第7页 
September 1991  
Revised November 1999  
74ACTQ18823  
18-Bit D-Type Flip-Flop with 3-STATE Outputs  
General Description  
Features  
The ACTQ18823 contains eighteen non-inverting D-type  
flip-flops with 3-STATE outputs and is intended for bus ori-  
ented applications. The device is byte controlled. A buff-  
ered clock (CP), Clear (CLR), Clock Enable (EN) and  
Output Enable (OE) are common to each byte and can be  
shorted together for full 18-bit operation.  
Utilizes Fairchild’s FACT Quiet Series technology  
Broadside pinout allows for easy board layout  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Guaranteed pin-to-pin output skew  
Separate control logic for each byte  
The ACTQ18823 utilizes Fairchild’s Quiet Series technol-  
ogy to guarantee quiet output switching and improved  
dynamic threshold performance. FACT Quiet Series fea-  
tures GTO output control and undershoot corrector for  
superior performance.  
Extra data width for wider address/data paths or buses  
carrying parity  
Outputs source/sink 24 mA  
Additional specs for Multiple Output Switching  
Output loading specs for both 50 pF and 250 pF loads  
Ordering Code:  
Order Number  
74ACTQ18823SSC  
74ACTQ18823MTD  
Package Number  
MS56A  
Package Description  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD56  
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
OEn  
Description  
Output Enable Input (Active LOW)  
Clear (Active LOW)  
Clock Enable (Active LOW)  
Clock Pulse Input  
CLRn  
ENn  
CPn  
I0I17  
O0O17  
Inputs  
Outputs  
FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010953  
www.fairchildsemi.com  

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