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74ACTQ16240 PDF预览

74ACTQ16240

更新时间: 2024-11-26 22:56:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
7页 73K
描述
16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs

74ACTQ16240 数据手册

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May 1991  
Revised November 1998  
74ACTQ16240  
16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs  
General Description  
Features  
Utilizes Fairchild’s FACT Quiet Series technology  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
The ACTQ16240 contains sixteen inverting buffers with 3-  
STATE outputs designed to be employed as a memory and  
address driver, clock driver, or bus-oriented transmitter/  
receiver. The device is nibble controlled. Each nibble has  
separate 3-STATE control inputs which can be shorted  
together for full 16-bit operation.  
Guaranteed pin-to-pin output skew  
Separate control logic for each byte  
16-bit version of the ACTQ240  
The ACTQ16240 utilizes Fairchild’s Quiet Series technol-  
ogy to guarantee quiet output switching and improve  
dynamic threshold performance. FACT Quiet Series fea-  
tures GTO output control for superior performance.  
Outputs source/sink 24 mA  
Additional specs for multiple output switching  
Output loading specs for both 50 pF and 250 pF loads  
Ordering Code:  
Order Number  
74ACTQ16240SSC  
74ACTQ16240MTD  
Package Number  
MS48A  
Package Description  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD48  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
Pin Assignment  
for SSOP and TSSOP  
Pin Descriptions  
Pin Names  
Description  
OEn  
Output Enable Inputs (Active Low)  
I0–I15  
O0–O15  
Inputs  
Outputs  
FACT , FACT Quiet Series , Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010924.prf  
www.fairchildsemi.com  

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