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74ACT86_01 PDF预览

74ACT86_01

更新时间: 2024-11-02 04:47:31
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
8页 186K
描述
QUAD EXCLUSIVE OR GATE

74ACT86_01 数据手册

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74ACT86  
QUAD EXCLUSIVE OR GATE  
HIGH SPEED: t = 5.0ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 2µA(MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS  
= 2V (MIN.), V = 0.8V (MAX.)  
50TRANSMISSION LINE DRIVING  
V
IH  
IL  
DIP  
SOP  
TSSOP  
T & R  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
DIP  
SOP  
74ACT86B  
74ACT86M  
V
CC  
74ACT86MTR  
74ACT86TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 86  
IMPROVED LATCH-UP IMMUNITY  
TSSOP  
The device is designed to interface directly High  
Speed CMOS systems with TTL, NMOS and  
CMOS output voltage levels.  
All inputs and outputs are equipped with protec-  
tion circuits against static discharge, giving them  
2KV ESD immunity and transient excess voltage.  
DESCRIPTION  
The 74ACT86 is an advanced high-speed CMOS  
QUAD EXCLUSIVE OR GATE fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS tecnology.  
The internal circuit is composed of 3 stages in-  
cluding buffer output, which enables high noise  
immunity and stabe output.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/8  

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