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74ACT74LCXR PDF预览

74ACT74LCXR

更新时间： 2024-01-16 02:05:14
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
10页 111K
描述
D Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, CQCC20, CERAMIC, LCC-20

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74ACT74LCXR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP14,.25
针数：14Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.48
Is Samacsys：N系列：ACT
JESD-30 代码：R-PDSO-G14JESD-609代码：e4
长度：5 mm负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：85000000 Hz
最大I（ol）：0.024 A位数：1
功能数量：2端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V传播延迟（tpd）：11 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：4.4 mm
最小 fmax：85 MHzBase Number Matches：1

74ACT74LCXR 数据手册

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November 1988  
Revised February 2005  
74AC74 • 74ACT74  
Dual D-Type Positive Edge-Triggered Flip-Flop  
General Description  
Features  
The AC/ACT74 is a dual D-type flip-flop with Asynchronous  
Clear and Set inputs and complementary (Q, Q) outputs.  
Information at the input is transferred to the outputs on the  
positive edge of the clock pulse. Clock triggering occurs at  
a voltage level of the clock pulse and is not directly related  
to the transition time of the positive-going pulse. After the  
Clock Pulse input threshold voltage has been passed, the  
Data input is locked out and information present will not be  
transferred to the outputs until the next rising edge of the  
Clock Pulse input.  
■ ICC reduced by 50%  
■ Output source/sink 24 mA  
■ ACT74 has TTL-compatible inputs  
Asynchronous Inputs:  
LOW input to SD (Set) sets Q to HIGH level  
LOW input to CD (Clear) sets Q to LOW level  
Clear and Set are independent of clock  
Simultaneous LOW on CD and SD makes both Q and Q  
HIGH  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74AC74SC  
M14A  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74AC74SC_NL  
(Note 1)  
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74AC74SJ  
M14D  
MTC14  
MTC14  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74AC74MTC  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74AC74MTCX_NL  
(Note 2)  
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74AC74PC  
N14A  
M14A  
M14A  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74ACT74SC  
74ACT74SC_NL  
(Note 1)  
74ACT74SJ  
M14D  
M14D  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74ACT74SJX_NL  
(Note 2)  
74ACT74MTC  
74ACT74PC  
MTC14  
N14A  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JECED J-STD-020B.  
Note 1: “_NL” indicates lead-free product (per JEDEC J-STD-020B).  
Note 2: “_NL” indicates lead-free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2005 Fairchild Semiconductor Corporation  
DS009920  
www.fairchildsemi.com  
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