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74ACT573

更新时间: 2024-11-12 22:56:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 锁存器输出元件
页数 文件大小 规格书
11页 237K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED)

74ACT573 数据手册

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74ACT573  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUTS (NON INVERTED)  
HIGH SPEED: t = 5ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4µA(MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS  
= 2V (MIN.), V = 0.8V (MAX.)  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
V
IH  
IL  
DIP  
SOP  
TSSOP  
T & R  
ORDER CODES  
PACKAGE  
|I | = I = 24mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
TUBE  
t
t
PLH  
PHL  
DIP  
SOP  
74ACT573B  
74ACT573M  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
74ACT573MTR  
74ACT573TTR  
V
CC  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 573  
IMPROVED LATCH-UP IMMUNITY  
When the LE is taken low, the Q outputs will be  
latched precisely or inversely at the logic level of D  
input data. While the (OE) input is low, the 8  
outputs will be in a normal logic state (high or low  
logic level) and while high level the outputs will be  
in a high impedance state.  
This device is designed to interface directly High  
Speed CMOS systems with TTL and NMOS  
components.  
DESCRIPTION  
The 74ACT573 is an advanced high-speed CMOS  
OCTAL D-TYPE LATCH with 3 STATE OUTPUT  
NON INVERTING fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
technology.  
2
These 8 bit D-Type latch are controlled by a latch  
enable input (LE) and an output enable input (OE).  
While the LE inputs is held at a high level, the Q  
outputs will follow the data input .  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/11  

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