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74ACT373MTR PDF预览

74ACT373MTR

更新时间: 2024-11-14 04:47:31
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
11页 241K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED)

74ACT373MTR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.03
Is Samacsys:N系列:ACT
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:11.5 ns
传播延迟(tpd):11.5 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

74ACT373MTR 数据手册

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74ACT373  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUTS (NON INVERTED)  
HIGH SPEED: tPD = 6ns (TYP.) at VCC = 5V  
LOW POWER DISSIPATION:  
ICC = 4µA(MAX.) at TA=25°C  
COMPATIBLE WITH TTL OUTPUTS  
V
IH = 2V (MIN.), VIL = 0.8V (MAX.)  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 24mA (MIN)  
BALANCED PROPAGATION DELAYS:  
tPLH tPHL  
OPERATING VOLTAGE RANGE:  
VCC (OPR) = 4.5V to 5.5V  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 373  
DIP  
SOP  
TSSOP  
T & R  
ORDER CODES  
PACKAGE  
TUBE  
DIP  
SOP  
74ACT373B  
74ACT373M  
74ACT373MTR  
74ACT373TTR  
TSSOP  
IMPROVED LATCH-UP IMMUNITY  
up at the D inputs. When the (OE) input is low, the  
8 outputs will be in a normal logic state (high or  
low logic level); when the (OE) input is high, the  
outputs will be in a high impedance state.  
This device is designed to interface directly High  
Speed CMOS systems with TTL and NMOS  
components.  
DESCRIPTION  
The 74ACT373 is a high-speed CMOS OCTAL  
D-TYPE LATCH with 3 STATE OUTPUT NON  
INVERTING fabricated with sub-micron silicon  
gate and double-layer metal wiring C2MOS  
technology.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
These 8 bit D-Type latch are controlled by a latch  
enable input (LE) and an output enable input (OE).  
When the (LE) input is high , the Q outputs follow  
the data (D) inputs . When the (LE) is taken low,  
the Q outputs will be latched at the logic levels set  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/11  

74ACT373MTR 替代型号

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