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74ACT373M PDF预览

74ACT373M

更新时间: 2024-11-13 22:56:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
10页 93K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

74ACT373M 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.04
Is Samacsys:N系列:ACT
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:11.5 ns
传播延迟(tpd):11.5 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

74ACT373M 数据手册

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74ACT373  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUT NON INVERTING  
HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 5V  
LOW POWER DISSIPATION:  
ICC = 8 µA (MAX.) at TA = 25 oC  
COMPATIBLE WITH TTL OUTPUTS  
V
IH = 2V (MIN), V = 0.8V (MAX)  
IL  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL =24 mA (MIN)  
BALANCED PROPAGATION DELAYS:  
tPLH tPHL  
OPERATING VOLTAGE RANGE:  
B
M
(Plastic Package)  
(Micro Package)  
ORDER CODES :  
74ACT373B  
74ACT373M  
(OE).  
While the LE inputs is held at a high level, the Q  
outputs will follow the data input precisely or  
inversely. When the LE is taken low, the Q  
outputs will be latched precisely or inversely at  
the logic level of D input data. While the (OE)  
input is low, the 8 outputs will be in a normal logic  
state (high or low logic level) and while high level  
the outputs will be in a high impedance state.  
This device is designed to interface directly High  
Speed CMOS systems with TTL and NMOS  
components.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
VCC (OPR) = 4.5V to 5.5V  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 373  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The ACT373 is an advanced high-speed CMOS  
OCTAL D-TYPE LATCH with 3 STATE OUTPUT  
NON INVERTING fabricated with sub-micron  
silicon gate and double-layer metal wiring C2MOS  
technology. It is ideal for low power applications  
mantaining high speed operation similar to  
equivalentBipolar Schottky TTL.  
These 8 bit D-Type latch are controlled by a latch  
enable input (LE) and an output enable input  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/10  
April 1997  

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